Note: I have graduated and moved on. This page is no longer up-to-date.
Dan Gibson on Google Sites.
My thesis work (here) explores the power/performance tradeoffs in future CMPs.
Much of my work has focused on a scalable core design, called
Forwardflow, which implements out-of-order execution using dynamically
scalable hardware. Interested readers can look at my Forwardflow TR, or my Forwardflow
ISCA paper, linked below.
Along with some unglamorous infrastructure work, I've been involved in a few other side projects along the way. In 2008,
I contributed to a paper on memory controller placement, which was eventually published in ISCA 2009. My work was on
the genetic algorithm used to explore the (very large) design space of memory controller configurations.
I also participated in a project with Randy Smith and Shijin Kong, reflecting on how parallel (software) packet classification
algorithms run on today's modern CMPs as compared to the semi-antiquated SMPs of yesteryear.
In the Summer and Fall of 2005, I implemented a memory consistency checker
for our simulation infrastructure, GEMS. Although GEMS uses Simics for functional simulation
and memory consistency (and is therefore sequentially consistent) we also wish
to verify that our processor and protocol simulators accurately model sequential
consistency timing characteristics. The consistency checker monitors the state
of the simulator, ensuring that the timings reported by GEMS
are not in violation if sequential consistency.
My previous work in Multifacet
was in performance optimization of Ruby, our memory timing model.
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