Main »

# Homework 1

Homework 1

I highly recommend getting started early!

The main objective of this problem set is to become familiar with the ModelSim program and the CS workstations. Before starting this homework you should do the following:

1. Follow the instructions on Getting started with Mentor to get your environment setup.
2. Read the Command-line Verilog Simulation Tutorial. Additional references are in the Tools page.
3. Read the Verilog Cheatsheet Verilog cheat. Everything you need to know about Verilog is in this document.
4. Read the Verilog file naming conventions pages and adhere to those conventions.
5. See Handin Instructions before getting started with homework.

You should simulate your solutions both to verify the correct function of your designs for yourself. You also have to hand in a copy of the Verilog files.

This assignment will take a significant amount of time if you are not already familiar with ModelSim and hardware design languages. Get started as soon as possible. In the 2nd week of class, there will be a lecture on Verilog.

To deal with complexity, use a "divide and conquer" or hierarchical design approach. Divide the circuit into logical pieces, called blocks, which can be composed to form the larger circuit. For example, a 4-to-1 multiplexor or mux can be composed from 2-to-1 muxes. Hierarchical design reduces both the complexity faced by the designer and the complexity of the computer's representation of the schematic. While hierarchical design may seem unnecessary for something as simple as a 4-to-1 mux, remember that modern computers have millions of gates.

Problem 1

1. Design a 1-bit 2-to-1 multiplexer module called mux2_1, using only NAND, NOR, and NOT gates.
• Implement the circuit in verilog using the provided basic gate modules. (See the Homework Modules Provided page.) These modules are already included in the downloaded folders. Instantiate them in your module to use them. Note that your implementation will be different than the one presented in the ModelSim Tutorial, because of this restriction.
• The input data lines of the multiplexer should be labeled InA and InB, the select line labeled S, and the output labeled Out.
2. Use the 2-to-1 mux you designed in step 1 to hierarchically create a 4-to-1 mux called mux4_1.
• Label the inputs InA, InB, InC, and InD, and the output Out.
• Make your select input a 2-bit-wide bus (not a single wire); name it S (1:0). (If S is b00, InA is selected; if S is b01, InB is selected, etc.)
• The inputs to the new mux should be four 4-bit busses labeled InA (3:0), InB (3:0), InC (3:0), and InD (3:0).
• The select bus is labeled S (1:0) and the output should be a bus labeled Out (3:0).
4. Use the testbench provided for testing.

#### What to submit:

• For electronic submission:
1. Submit all the verilog files. See instructions here.
2. Make sure you run the Verilog rules check on all the files. Not necessary to run it on your testbench.

Problem 2

1. Design a 1-bit full adder called fulladder, using only NOT, NAND, NOR, and XOR gates. (Again use the provided gate modules).
• Label the inputs as A, B and Cin (carry-in). Label the outputs as S (sum) and Cout (carry-out).
2. Optionally verify the correctness of your 1-bit adder over all combinations of inputs by writing your own test bench. It is generally the best to test at the smallest module level first. Follow the provided test bench as guidance. (This small test bench is for your debugging. You can (and actually have to) use some keywords which are prohibited in module implementation.)
3. Using the 1-bit full adder you created above, design a ripple carry adder that adds two 4-bit binary numbers. Call it fulladder4.
• Make the inputs and outputs 4-bit busses labeled A (3:0), B (3:0), CI (carry-in), SUM (3:0), and CO (carry-out).
4. Using the 4-bit full adder you created above, design a ripple carry adder that adds two 16-bit binary numbers. Call it fulladder16.
• Make the inputs and outputs 16-bit busses labeled A (15:0), B (15:0), SUM (15:0), and CO (carry-out).
• This fulladder16 module as a whole does not take in a carry-in input.
5. Think about how your design might be simpler if you only needed to compute A+1 rather than A+B. No submission is necessary for this.
6. Use the testbench provided for testing.

#### What to submit:

• For electronic submission:
1. Submit all the verilog files. See instructions here.
2. Make sure you run the Verilog rules check on all the files. Not necessary to run it on your testbench.

Problem 3

A sequence detector is a finite state machine that outputs "1" when a particular sequence is detected and outputs "0" otherwise. For example, a sequence detector designed to detect the sequence "1010" outputs "1" every time this sequence is seen in the input stream. Thus, for an input stream "101010" the output will be "0000101".

Design a sequence detector that detects two specific digits represented in binary coded decimal (BCD). Your design should sample a one bit input InA at the rising edge of a clock signal Clk. Use the Reset signal to initialize any registers you may use. Select the sequence to detect from the following table, using the least significant digit in your UW ID number. For example, if your id is 902 631 9385 , the least significant digit is 5, so you should select the sequence 85, which is 10000101 in BCD. The sequence detector should also detect overlapping sequences.

NOTE: You are expected to implement a Moore machine (and not a Mealy machine). Quick reference here.

 Last digit (of UW ID) Sequence 0 or 5 85 1 or 6 97 2 or 7 42 3 or 8 53 4 or 9 28

You should complete each of the following:

• Construct the state diagram of the machine - make sure you draw this on paper. Even though we are NOT going to require you to turn it in.
• Implement the sequence detector using Verilog. Call it seqdec_<your_two_digits>. E.g., if you are implementing a sequence detector for the sequence 42 , then call your module seqdec_42.
• It takes three inputs: InA (next bit in the stream), Clk (clock signal), and Reset.
• It has one output: Out.
• Assume that your detector has seen a stream of zeros at the beginning.