Homework 2
This semester we will not do assignments in partners. Please ignore the downloaded partners.txt
file.
Be sure that you have:
- Read the Command-line Verilog Simulation Tutorial. Additional references are in the Tools page.
- Read the Verilog Cheatsheet Verilog cheat. Everything you need to know about Verilog is in this document.
- Read the Verilog file naming conventions and the Verilog rules, and adhere to these rules.
- See Handin Instructions before getting started with this homework.
For each problem, follow these steps:
- Break down your design into sub-modules.
- Define interfaces between these modules.
- Draw paper and pencil schematics for these modules.
- Then start writing Verilog.
What to submit:
- Problems 1 & 2:
- Submit all the verilog files. See instructions here.
- Make sure you run the Verilog rules check on all the files. Not necessary to run it on your testbench.
Problems 3 - 15 are optional and will not be submitted. These are recommended for a better understanding of course material.
Download Files
- Required files in this tar file <<<DOWNLOAD THIS FIRST
- Problem 1 and 2 are in its own directory, called hw2_1, hw2_2.
- Do not edit the provided
*_hier.v
files.
Problem 1
Design a 16-bit barrel shifter called shifter
in shifter.v
with the following interface. Consult lecture notes for barrel shifter design.
Inputs:
[15:0] In
- 16 bit input, value to be shifted
[3:0] Cnt
- 4 bit amount to shift (number of bit positions to shift)
[1:0] Op
- shift type, see encoding in table below
Output:
[15:0] Out
- 16 bit output
Opcode | Operation |
00 | rotate left |
01 | shift left |
10 | shift right arithmetic |
11 | shift right logical |
Do NOT use Verilog logical shift operators for this problem. Design a barrel shifter using muxes.
Verify your design using the given testbench. A correct design should yield a TEST PASSED
message in the testbench output.
Problem 2
Design a simple 16-bit ALU called alu
in alu.v
. Operations to be performed are 2's Complement ADD, bitwise-OR, bitwise-XOR, bitwise-AND, and the shift unit from problem 1. In addition, it must have the ability to invert either of its data inputs before performing the operation and have a Cin input (to enable subtraction). Another input line also determines whether the arithmetic to be performed is signed or unsigned.
Use a carry look-ahead adder (CLA) in your design. (Hint: First design a 4-bit CLA. Then use blocks of this CLA for designing the 16-bit CLA.) For all the shift and rotate operations, assume the number to shift is input A
to ALU and the shift/rotate amount is bits [3:0]
of input B
.
Opcode | Function | Result |
000 | rll | rotate left |
001 | sll | shift left |
010 | sra | shift right arithmetic |
011 | srl | shift right logical |
100 | ADD | A+B |
101 | OR | A OR B |
110 | XOR | A XOR B |
111 | AND | A AND B |
The external interface of the ALU should be:
Inputs:
[15:0] A
, [15:0] B
- Data input lines A and B (16 bits each)
Cin
- A carry-in for the LSB of the adder
[2:0] Op
- The OP code (3 bits). It determines the operation to be performed. The opcodes are shown in the table above
invA
- An invert-A input (active high) that causes the A input to be inverted before the operation is performed
invB
- An invert-B input (active high) that causes the B input to be inverted before the operation is performed
sign
- A signed-or-unsigned input (active high for signed) that indicates whether signed or unsigned arithmetic to be performed for ADD function on the data lines. This affects the Ofl
output
Outputs:
[15:0] Out
- Data out (16 bits)
Ofl
- This bit is high if an overflow occurred
Zero
- This indicates that the result is exactly zero
Other assumptions:
- You can assume 2's complement numbers for signed numbers.
- In case of logic functions,
Ofl
is not set.
Simulate and verify your design using the supplied testbench or create one yourself to test any of your submodules. You must reuse the shift unit designed in Problem 1.
The remaining problems will not be submitted but are recommended for a better understanding of course material.
Problem 3
Do problem 1.3 from textbook
Problem 4
Do problem 1.4 from textbook
Problem 5
Do problem 2.1 from textbook
Problem 6
Do problem 2.2 from textbook
Problem 7
Do problem 2.3 from textbook
Problem 8
Do problem 2.14 from textbook
Problem 9
Do problem 2.15 from textbook
Problem 10
Do problem 2.16 from textbook
Problem 11
Do problem 2.17 from textbook
Problem 12
Do problem 2.18.1 to 2.18.3 from textbook
Problem 13
Do problem 2.19.1 to 2.19.3 from textbook
Problem 14
Do problem 2.25.1 to 2.25.2 from textbook
Problem 15
Do problem 2.26.1 to 2.26.3 from textbook