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# Homework 3

Homework 3

This semester we will not do assignments in partners. Please ignore the downloaded `partners.txt` file.

Be sure that you have:

1. Read the Command-line Verilog Simulation Tutorial. Additional references are in the Tools page.
2. Read the Verilog Cheatsheet Verilog cheat. Everything you need to know about Verilog is in this document.
3. Read the Verilog file naming conventions and the Verilog rules, and adhere to these rules.
4. See Handin Instructions before getting started with this homework.

For each problem, follow these steps:

2. Define interfaces between these modules.
3. Draw paper and pencil schematics for these modules.
4. Then start writing Verilog.

### What to submit:

• Problems 1, 2 and 3:
1. Submit all the verilog files. See instructions here.
2. Make sure you run the Verilog rules check on all the files. Not necessary to run it on your testbench.

Problems 4 - 10 are optional and will not be submitted. These are recommended for a better understanding of course material.

• Problem 1, 2, and 3 are in its own directory, called hw3_1, hw3_2, hw3_3.
• Do not edit the provided `*_hier.v` files.

Problem 1

Using Verilog, design a register file called `rf` in `rf.v`. This register file consists of 8 registers, each 16-bit wide. It has one write port, two read ports, three register select inputs (two for read and one for write), a write enable, a reset, and a clock input. All register state changes occur on the rising edge of the clock. As always, your basic building block must be the `dff` module provided. The read ports should be all combinational logic. Do not use tri-state logic in your design.

Note: Design this register file such that changing the width to 32-bit or 64-bit is straightforward.

Ports:

• The read and write data ports are 16 bits each.
• The select inputs (read and write) are 3 bits each.
• When the write enable is asserted (high), the selected register will be written with the data from the write port.
• The write occurs on the next rising clock edge;
• Written data cannot flow through to a read port during the same cycle.
• There is no read enable; data from the selected registers will always appear on the corresponding read ports.
• The reset signal is synchronous and, when asserted (high), resets all the register values to 0.
• The `err` output is a standard way of indicating hardware errors or illegal states. Assert it (`1'b1`) for states which are supposed to be impossible to get into.

You must use a hierarchical design. Design a 16-bit register first, then put 8 of them together with additional logic to build the register file.

The testbench for this problem (`rf_bench.v`) generates a random set of input signals to your module in each cycle, and compares outputs from your module with outputs that are expected from a perfect register file implementation.

If there are no errors in your design you will see a "TEST PASSED" message. If the testbench failed with a "TEST FAILED" message, look for error messages like "ERRORCHECK: Incorrect read data in cycle <cycle_number>" in the testbench output. Above each of these error messages, you will see the inputs to your module, your outputs, and the expected outputs for that cycle which can help you debug.

Problem 2

Using Verilog, design a six-state saturating counter. The counter should take as input a clock, a global clock reset (`rst`), and a reset line (`ctr_rst`). It has a 3-bit wide output and an err output.

Inputs:

• Reset is synchronous and sets the output to 0 at the rising edge of the clock.
• The `ctr_rst` signal is not the same as the global reset signal generated at the start of a simulation.
• Use the global `rst` signal to initialize the state of the counter to zero;
• The `ctr_rst` line is active high, i.e., a logical value of 1 will reset the counter to 0, while a logical value of 0 will let the counter increment;
• All state changes should occur on the clock's rising edge.

Outputs:

• Output should increment every clock cycle until it reaches its saturation value (5, i.e., 101 in binary) and then continue to output the maximum value until reset.
• The `err` output is a standard way of indicating hardware errors or illegal states. Assert it (`1'b1`) for states which are supposed to be impossible to get into.

The testbench for this problem (`sc_bench.v`) randomly asserts `ctr_rst` and compares outputs from your module with outputs that are expected from a perfect saturating counter implementation.

If there are no errors in your design you will see a "TEST PASSED" message. If the testbench failed with a "TEST FAILED" message, look for error messages like "ERRORCHECK: ctr_rst = xx : out = xx : expected_out = xx" in the testbench output. These lines show the input to your module (`ctr_rst`), your output, and the expected output which can help you debug.

Problem 3 - Part (a)

In Verilog, create a register file that includes internal bypassing so that results written in one cycle can be read during the same cycle. Do this by writing an outer "wrapper" module called `rf_bypass` in `rf_bypass.v` that instantiates your existing (unchanged) register file module `rf` from Problem 1. Your new module will just add the bypass logic.

The list of inputs and outputs of the outer module should be the same as that of the inner module described in Problem 1.

The testbench for this problem (`rf_bypass_hier_bench.v`) generates a random set of input signals to your module in each cycle and compares outputs from your module with outputs that are expected from a perfect register file bypass implementation.

If there are no errors in your design you will see a "TEST PASSED" message. If the testbench failed with a "TEST FAILED WITH xx ERRORS" message, look for error messages like "ERRORCHECK: Read data incorrect in cycle <cycle_number>" in the testbench output. Above each of these error messages, you will see the inputs to your module, your outputs, and the expected outputs for that cycle which can help you debug.

Problem 3 - Part (b)

Read the synthesis tutorial on the Synthesis page.

• Synthesize your new register file (in the same `hw3_3` directory).
• Synthesis will create a `synth` directory which will include `rf_bypass.syn.v`, area report, timing report, etc. Do not delete this directory - it must be included in your submission.
• Make sure that:
• NO cells in the `synth/cell_report.txt` has zero area in it. If you see a zero area for a module name, then that means that module had some kind of Verilog coding error and did NOT get synthesized. You must fix this problem. Look in `synth.log`, search for that module name, and look for warnings/errors.
• NO cells in the `synth/reference_report.txt` has zero total area. If it does, then some sub modules underneath have failed to synthesize. Check `cell_report.txt`.

The remaining problems will not be submitted but are recommended for a better understanding of course material.

Problem 4

Do problem 4.7

Problem 5

Do problems 4.8

Problem 6

Do problem 4.9

Problem 7

Do problems 4.1.1 to 4.1.3 in page 357 of textbook.

For 4.1.1, In addition to the control signals RegWrite, ALU operation, MemWrite, MemRead and Branch, you should also report the control signals of the following two control signals:

• ALUMux: the control signal that controls the Mux at the ALU input, 0 (Reg) selects the output of the register file and 1 (Imm) selects the immediate from the instruction word as the second input to the ALU.
• RegMux: the control signal that controls the Mux at the data input to the register file, 0 (ALU) selects the output of the ALU, and 1 (Mem) selects the output of memory.

Problem 8

Consider a single-cycle computer design such as the one in Figure 4.15 of text (page 263). Assume a MIPS-like instruction set. Suppose you had just completed such a design, and now the compiler group has come to you with a small list of additional instructions they would like you to add. How would you respond? Order the list from easiest to most difficult to add, based on the number of things that would have to change in the datapath; briefly indicate for each one what those changes would be.

1. "Split Register": This instruction would read an operand from \$rs and move its lower half to \$rd with the upper half set to zero. It would also take the upper half of \$rs, shift it right 16 bits (with zero fill), and write it to \$rt.
2. "Bit Equal": This instruction does a bit-for-bit compare between two registers. For each bit i, if bit i of \$rs is equal to bit i of \$rt, set bit i of \$rd; otherwise set bit i of \$rd to zero.
3. "Replace Under Mask": This I-Format instruction uses the 16-bit sign-extended immediate to select which bits of \$rt should be replaced with the corresponding bits of \$rs. For each bit of the sign-extended immediate that is a one, the result comes from the corresponding bit of \$rs; for each bit that is a zero, the result comes from \$rt. The result is written to \$rt.

Problem 9

For this problem, you do not need to use mentor or Verilog; just draw the designs (neatly!) on paper.
First, design a 4-bit ripple-carry adder; as a building block use squares representing full adders. (You may use a printout from Homework 1.)
Next, draw an 8-bit carry-select adder, using as building blocks (three) 4-bit ripple-carry adders and 2:1 muxes.

Now, calculate the delay at output S5 of the carry-select adder. To do this, you will need to know the gate design of the full adder and the 2:1 mux (see below). You will also need to know the delay function:
AND, OR, NAND, NOR, NOT: delay = (8 + n2) τ
XOR: delay = (12 + n2) τ
where n is the number of inputs to the gate.
Assume that all inputs to your design are available at time zero. Calculate (and mark on your paper) the pertinent critical-path delays through the basic building blocks, through your ripple adder, and finally to S5 of the entire design.

Problem 10

This problem does not require verilog implementation. You should work to create a neatly drawn schematic.

Consider the division algorithm in Figure 3.10 (page 238) of the text and the accompanying high level diagram in Figure 3.9 (page 237). For this problem create a working and detail schematic with hierarchical design implementing this bit-wise divider. Simply reproducing Figure 3.9 will earn you negative points :-)

If you feel there is ambiguity in the problem specification, make reasonable assumptions and start your answer stating all your assumptions.

• The schematic should include
• The names and bit widths of external ports of the design
• Think about how the values of dividend and divisors are going to be initialized.
• Do you need any control signals for the inputs?
• Do you need any output ports?
• How would another module interact with the divider module? Do you need a control signal to notify that the divide operation is completed?
• The name for each block
• The names and bit widths of interfaces between blocks.
• You will be graded based on:
• the correctness of the design
• the completeness of the design
• If a team of 4-5 engineers were to implement (each person in charge of one block) the design in verilog, your design document would function as a reference for this team. They should be able to complete the implementation without talking to you or talking to each other. This requires that the interfaces are marked clearly, with meaningful names and bit widths.