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Problems 1: Tentatively removed - no submission is required for this homework.
Problems 2 - 6 are optional and will not be graded. These are recommended for a better understanding of course material.
Consider the example single-error-correcting code with a minimum Hamming distance of three example in the ECC1 handout. The handout can be found at the bottom of this page
This is a good reference on IEEE 754 standard; link
Virtual Memory: Consider a byte addressable system with 1GB physical memory and 4GB of virtual address space and no caching.
1) What should be the width of the address bus within the processor (prior to address translation)? What should be the width of the address bus after address translation?
2) Assume that the system uses 4KB pages. How many page table entries are required per process, (assuming that all processes uses all 4GB of the virtual address space)?
3) Now we are adding a TLB to speed up address translation. The TLB is fully associative with only four entries. The snapshot of the TLB and the contents of the relevant portion of the page table are shown below. Explain why the tags are 20 bits wide and why the physical page numbers are 18 bits wide.
TLB snapshot: (:notabledit:)
Page table snapshot: (:notabledit:)
Consider the same system of Problem 6 and the snapshot of TLB and page tables for a given process.
1) Given that this process generates the following stream of virtual addresses:
Classify each access as TLB hit/Page table hit/Page fault.
2) For each memory access which is not a page fault, what is the translated physical address?
What are types of programs or problems that are not suitable for GPUs? Give one example. You may describe an algorithm, psuedo-code or c-code. Justify why you think that the performance of this algorithm will be bad on GPUs.
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