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CS552 Course project
Course Project Overview
The CS552 term project is the complete functional design of a microprocessor called the WISC-SP13. All components of your design will be written in Verilog. As with the course homework assignments, the CS552 Verilog rules apply and all final code is expected to pass the Vcheck program.
Your processor will support the WISC-SP13 ISA, as described in the ISA Specification page.
Each stage of the design makes the processor progressively more complicated. For your own benefit, it is strongly recommended that you not proceed to a new stage before you are confident the current stage is working. Debugging errors in a complex design can quickly diminish your level of enjoyment during the project.
Many of the Verilog problems in the homework assignments were designed to be compatible with the project. Please feel free to reuse these modules (of course, fixing any errors first!). In addition to the previous homework problems, you will be provided with several reusable modules that you can use in your design. Most of these are Verilog implementations of memory system components. Please note that these files do not follow the CS552 Verilog restrictions, so no need to include them when you run Vcheck.
An assembler for the WISC-SP13 ISA is provided for your use. Sample test programs are also provided, although you are strongly encouraged to write custom tests to augment these. Be aware that these test programs were written for a slightly different ISA specification and therefore may not work as advertised. It will be your job as diligent designers to determine if unexpected behavior occurs due to a bug in your design or as the result of the change in ISA.
We recommend you to:
If you finish really early, you will get the opportunity to possibly map your design (or a part of it) to an FPGA chip.
If you are able to complete this project without the unnecessary stress that procrastination imposes, it is our belief that you will find this to be a highly rewarding experience.
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