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Project Steps & Grading
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There are four major deadlines over the course of your term project design, which will be met in the form of project demos with the course TA and a final project report. The project will be done individually this semester.
Everyone should be well prepared before showing up to a demo. Time is limited and your grade may be negatively impacted if the demo could not be completed. Be sure that the designs you hand in work without alteration in such a way that the TA could easily compile and simulate the design without special instructions.
You can think of this project as having roughly six stages of development with several demos along the way.
Each student needs to turn in a typed report (one to two page single-spaced) describing your project design and test plan. You are expected to develop a detailed schedule identifying key milestones. Make sure that your schedule takes into account the remaining homework assignments and your other course obligations (e.g., midterms).
You must have thought about the design at a high level. The plan you come up with will be your master plan for the semester and you might be asked to update/revise the plan as we go along. In addition to the design, you are expected to develop a detailed test plan, including high-level descriptions of components, modules, and tests.
Look through the calendar for design review, demo-1, demo-2, and cache demo deadlines and plan your work accordingly. These dates are non-negotiable and you must adhere to them. There will be a signup for a 10-minute meeting for design review. Depending on how things shape up, we may do signup and meetings for demo-1, demo-2, and cache-demo also.
Each student needs to create a complete hand-drawn (or drawn with the aid of a graphing program like Openoffice draw) schematic of an unpipelined WISC-SP13 implementation. Each module, bus, and signal should be uniquely labeled. The schematic should be hierarchical so that the top-level design contains only empty shells for each planned submodule. In general, there will be a one-to-one mapping of modules in your schematic to the modules you will eventually write in Verilog. The textbook pipeline diagram is a good starting point but there are many differences between it and the ISA for this project. You will need to look at the WISC-SP13 ISA specification and make sure to adapt it to that.
While explicitly drawing pipeline stages in the schematic is not required, you should still design with a pipeline in mind. It is a good idea to place modules near their final location in the pipelined design.
We will go through your Canvas submissions and give comments as feedback. For incomplete submissions (or submissions with potentially serious flaws), we will arrange one-one meetings to help you catch up with the project pace. Not necessary to have done a complete table of signals, but if you have such a table with the control signal values for every instruction, that would be great.
Design a single-cycle, non-pipelined WISC-SP13 processor. For this stage, you will use the single-cycle perfect memory. Since you will need to fetch instructions as well as read or write data in the cycle, use two separate memories -- one for instruction memory and the other for data.
Your design should be running the full WISC-SP13 ISA, except for the extra-credit instructions. It should use a single-cycle memory model. Your modules must all pass Verilog rules check.
It is highly recommended to modularize your design. Put each of the 5 MIPS stages into a separate sub-high-level module. In this unpipelined version, your
In the demo, you will run a set of programs on your processor using the
A message of "SUCCESS" means test passed. Run all the categories and rename the
Notes on Grading:
What to submit:
Since your single-cycle design must fetch instructions as well as read or write data in the same cycle, you will want to use two instances of this memory -- one for data and the other for instructions. You should instantiate this memory module twice. One instance will serve as the instruction memory while the other will serve as the data memory. Note that the program binary should be loaded into both instances. This will indeed be done (without any additional effort from your side) if you use the same module definition for both instances.
+-------------+ data_in[15:0] >-------| |--------> data_out[15:0] addr[15:0] >-------| 65536 word | enable >-------| by 8 bit | wr >-------| memory | clk >-------| | rst >-------| | createdump >-------| | +-------------+
During each cycle, the
The memory is initialized from a file, "
@0 12 12 12 12
where "@0" specifies a starting address of zero, and "12" represents any 2-digit hex number. Any number of lines may be specified, up to the size of the memory. The assembler will produce files in this format.
At the end of a simulation, the memory can produce a dump file so that you may check what has been written to the memory. When
0000 1234 0001 1234 0002 1234
Examining the source file
When you have two copies of the memory, one for instructions and the other for data, you may want to let both memories load the same load file, but only have the data memory generate a dump file.
The way to load a program for your processor is using the assembler, which will create a memory image of assembled machine code (named
For this demo, a pipelined version of your design needs to be running correctly, but no optimizations are needed yet. "Correctly" means that it must detect and do the right thing on pipeline hazards (e.g., stalling). You will still use the single-cycle perfect memory model. We will follow a similar protocol as demo1. I will run your tests and ask teams with any failures to signup for a demo with me.
We recommend that you write at least two additional hand tests to test for pipelining. This will help simplify debugging. If you write additional tests, include them in
You must also submit a document named titled
The Instruction Retired field would either be one of the instructions from the test program or a "
Again, you should also include a bunch of
Notes on Grading:
What to submit:
All information on cache design can be found on the Cache Design page.
What to submit:
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