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Verilog Rules Check

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Verilog Rules Check Script

A Java program Vcheck will be used to scan your design for some of the common illegal constructs. It is fairly simple, and can be easily fooled into either allowing things or complaining incorrectly. But it is a useful tool if you are unclear as to whether or not your design meets the requirements set forth here. You will be required to run it on your Verilog designs and hand in the output; To run it, copy the two class files Vcheck.class and VerFile.class into a directory, and from that directory type:

prompt> "java Vcheck <myfile.v>"

For every Verilog file, run this tool and save the output in a file with the extension .vcheck.out. For example, if you had a file called add.v, then your vheck output file should be add.vcheck.out. The .vcheck.out files should be turned in.

Automated scripts

From the UNIX prompt on a CS machine, cd to the directory where your Verilog files are and issue the following command:

prompt> myfile.v myfile.vcheck.out

If there are no errors, the vcheck.out file will contain a string like the following:

End of file /tmp/foo.v. Hash = 377189683

If there are errors, you will see them in the vcheck.out file. For example:

Line 5: Expected '@' after 'always' Line 5: Always without case(x) End of file /tmp/foo.v. Hash = -994087497

To run vcheck on all the Verilog files in a directory:


This script will run vcheck on all the Verilog files in your current directory and generate .vcheck.out files for each Verilog file.

Page last modified on October 03, 2020, visited times

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