Project Modules Provided

You may use the the following pre-built Verilog modules in your project. These do not follow the Verilog rule, so do not run Vcheck on them.

• D-FlipFlop: verilog source
• Clock-Reset Module: verilog source; updated 03/04/2008.
• Single Cycle Perfect Memory; updated March 18, 2007
• Aligned single Cycle Memory
• Stalling Memory
• Four-banked Memory Module
  • updated, memory4c_042208.v
• Cache Module
• Register file verilog testbench for HW3: Usage instructions.
  1. Version 1.0 verilog source
  2. Version 1.1 source code, bugs fixed from version 1.0
     1. Reference design ignores reset and writes to register file during reset
     2. Reference design and testbench passes through writes to reads in same cycle.
• Register file verilog testbench for HW4 with internal bypassing: verilog source.
• Memory system verilog testbench for HW5: tar ball.
  • Updated mem_system_perfbench.v - includes a log of hit/miss for every cache access. mem_system_perfbench_042108.v
  • Updated mem_system_randbench.v - createdump is now connected at top level. mem_system_randbench_042108.v
  • Updated mem_system_perfbench.v - includes support for comments. Any line that begins with a // or # is a comment. Use at own risk. mem_system_perfbench_042908.v
  • Updated MAJOR BUG in mem_system_perfbench.v. mem_system_perfbench_050308.v

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• Processor hier top level with clock generator. You MUST use ONLY this top. NO modifications allowed. proc_hier.v verilog source code. Modified May 04, 2008
• Your processor top-level module must be called proc and must be in a file called proc.v. You MUST modify this file and instantiate sub-modules and such inside it. proc.v verilog source code. Modified May 04, 2008
• Processor top level testbench. You MUST use this test bench. You may make modifications if necessary. proc_hier_bench.v verilog source code. Modified May 04, 2008
  • For the demos and before final submission you MUST edit lines 57 to 65 and make those wire assignments.
  • As you can see this testbench prints a log of all writes to the register file, reads from data memory, and writes to data memory.

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• Processor top level testbench for pipelined processor.
  proc_hier_pbench.v verilog source code. Modified 04/10.
  You must run wsrun.pl with the -pipe option
  Modified 05/03 and added support for DHIT_RATE and IHIT_RATE