Stalling Memory

Stalling Memory Specification

After you have successfully made a pipelined version of your processor, the next step will be to make your design capable of handling arbitrary stalls in the memory accesses. To do this, replace your single-cycle memory modules with these "stalling memory" modules. verilog source

This module has a "ready" output. When "enable" is true, "ready" may be either true (indicating that the requested read or write has been done), or false (indicating that read data is not valid or that a write has not been performed). Your design must keep presenting the same operation to the memory module until the operation succeeds.

                              +-------------+
       data_in[15:0]  >-------|             |--------> data_out[15:0]
          addr[15:0]  >-------|  65536 word |--------> ready
              enable  >-------|  by 16 bit  |
                  wr  >-------|  memory     |
                 clk  >-------|             |
                 rst  >-------|             |
          createdump  >-------|             |
                              +-------------+

Examining the source file stallmem.v, you will see "rand_pat", a shift register which controls the "ready" output. This is a random 32-bit number. You can changes its value by changing the seed used for random number of generation. You can do this by passing in "-seed" to wsrun.pl. For example:

wsrun.pl -seed 45 -prog foo.asm proc_hier_pbench *.v

If you are executing from inside ModelSim with run -All or using a testbench of your own for preliminary testing, you can pass in the seed, by adding the string "+seed=<value>" to the vsim command. Or simply edit stallmem.v and set the seed to a different value.