Tools

This course will use the Mentor tool suite.

• Getting started with Mentor
  • Errata to getting started document
  • Documentation on Mentor in the CS environment
  • Using Mentor remotely
• Simulating Verilog Tutorial : Recommended approach for this course. We will use ModelSim.
• Command-line Verilog Simulation Tutorial
• Verilog rules : You shall not deviate from rules in this document
• Vcheck.class, VerFile.class
• Verilog Rules Check
• Simulating Verilog modules using QuickSimII with schematics : Use at own RISK
• WISC-SP08 Simulator-debugger
• Using the assembler
• Tools FAQ
• Miscellaneous hardware design documentation. Information is for reference, some things may not work in our current environment.
  • Mentor tools overview
  • Mentor tool overview from Santa Clara University
• Sharing files between project members