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No. You may not. At first this may seem to be ok, but when project starts and other homeworks come up, the inconsistencies between the CS and CAE machine will become too complicated to handle. In spite of this note, if you insist on using the CAE machines, you are welcome to, but will get no tool support from me or the TA.
See the student wiki entry here
Set both to 1(Vcc).
Instead of using the wires one can rip it using a bus ripper. There is an option rip in gen_lib to do this.
To connect individual lines of an 16 bit wide bus we need 16x1 ripper.
To connect the ripper to the bus follow the steps below:
6. How do I show a simulation and Mentor tools running on my screen to the TA (or another person) to troubleshoot a problem?
Use x11vnc which will export an existing display using vnc. Say you are logged in on emperor01.cs.wisc.edu, and you have the tools running and you are stuck at a problem you want to show the TA. At the shell prompt, type:
prompt % /u/k/a/karu/local/bin/x11vnc -display :0
prompt % vncviewer emperor01.cs.wisc.edu:5900
Voila - you should see the display of emperor01.cs.wisc.edu exported as a vnc session.
If you are having license issues starting vsim, please type the following command:
setenv MGLS_LICENSE_FILE /s/mentor/etc/cust/mgls/mgc.licenses on your csh shell and hit "vsim".
8. Should an unaligned memory access cause the processor to die immediately, or should it turn the memory access into a halt instruction in the memory stage and exit more "gracefully"?
You do NOT need to implement any graceful degradation behavior here. Just OR together all your err signals and propagate up to the top-level, which will cause the simulation to abruptly die without preserving any clean semantics about which instruction retired last etc. This is OK.
For these tests, you will most likely get a fail message because the output from verilog simulation and wiscalculator will not match.
Yes - this is a suggested design flow only. If your stalling memory works, you can skip this recommended stage 3.3 and directly integrate your mem_system_hier developed for homework 5 into your processor.
a) It varies from program to program b) I expect you to write a small set of programs to demonstrate ideal CPI and also possibly really bad CPI.
On the provided set of tests you will notice the CPI varies considerably.
|Page last modified on May 03, 2008|