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Aligned Single Cycle Memory


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Aligned Single-Cycle Memory Specification

Before building your cache, you should use this memory to update and test your processor's interface to properly handle unaligned accesses. Many processors (e.g., MIPS) are byte addressable, but require that all accesses be aligned to their natural size (i.e., byte loads and stores can access any individual byte, but word loads and stores must access aligned words). Since your processor only has word loads and stores, this is pretty simple (to support byte stores, the memory would need byte write enable signals; to support byte loads, either the memory or the processor needs a mux to select the right byte). Notice that the memory always returns aligned data even on a misaligned load.

verilog source code, synthesizable version.

Since your single-cycle design must fetch instructions as well as read or write data in the same cycle, you will want to use two instances of this memory -- one for data, and one for instructions.

data_in[15:0] >-------| |--------> data_out[15:0] addr[15:0] >-------| 65536 word | enable >-------| by 16 bit |--------> err wr >-------| memory | clk >-------| | rst >-------| | createdump >-------| | +-------------+

During each cycle, the "enable" and "wr" inputs determine what function the memory will perform. On a unaligned access err is set.

0XNo operation00
11WriteWrite data_in0
1XXif (data[0]) set1

Page last modified on March 03, 2011, visited 1327 times

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