|CS552 Course Wiki: Spring 2013||Main »
cachesim is a cache simulator which simulates a cache based on its input parameters. It has four/five inputs:
uses pseudo random replacement instead.
For example to simulate the direct-map cache designed in HW5, you should use cachesim as follows:
You can use any of test traces and assign its path as the last input parameter to cachesim.
To simulate 2-way set associative cache you have designed in Hw 5, you should use cachesim in this way:
cachesim shows actions happening in the defined cache after running each line of the trace input file. Example running:
Which are the actions happening when running mem5.addr (one load to 348 and one load to 2396)
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