Main »

# Homework 1

### Due 02/07.Weight: 20%

I highly recommend getting started early!

The main objective of this problem set is to become familiar with the ModelSim program and the CS workstations. Before starting this homework you should do the following:

1. Follow the instructions on Getting started with Mentor to get your environment setup.
2. Read the Simulating Verilog Tutorial, Go through the ModelSim Tutorial, at least through step five. (Additional Mentor documentation is available on-line as part of the Mentor help system, or here.)
3. Read the Verilog rules document, which describes the allowable subset of verilog that you are to use. You will use a program called Vcheck to ensure that you have followed these restrictions. You can read about Vcheck at the bottom of the Verilog rules document.
4. Read the Verilog file naming conventions pages and adhere to those conventions.

You should simulate your solutions both to verify the correct function of your designs for yourself and to hand in to me so that I can see that your solutions work. You also have to hand in a copy of the verilog files.

This assignment will take a significant amount of time if you are not already familiar with ModelSim and hardware design languages. Get started as soon as possible. In the 2nd week of class, there will be a lecture on Verilog.

To deal with complexity, use a "divide and conquer" or hierarchical design approach. Divide the circuit into logical pieces, called blocks, which can be composed to form the larger circuit. For example, a 4-to-1 multiplexor or mux can be composed from 2-to-1 muxes. Hierarchical design reduces both the complexity faced by the designer and the complexity of the computer's representation of the schematic. While hierarchical design may seem unnecessary for something as simple as a 4-to-1 mux, remember that modern computers have millions of gates.

Problem 1

1. Design a 1-bit 2-to-1 multiplexer using only NAND, NOR, and NOT gates. Implement the circuit in verilog using these modules. These modules can be found in the Homework Modules Provided page. Note that your implementation will be different than the one presented in the ModelSim Tutorial, because of the restrictions. The input data lines of the multiplexer should be labeled InA and InB, the select line labeled S, and the output labeled Out.
2. Simulate the multiplexer over all possible combinations of inputs. You can do this by applying clocks of different periods to each input and then running the simulation long enough for all combinations to appear. Handin the simulations.
3. Use the 2-to-1 mux you designed in step 1 to hierarchically create a 4-to-1 mux. Label the inputs InA, InB, InC, and InD, and the output Out. Make your select input a bus (not single wires); name it S(1:0) (If S is 00, InA is selected; if S is 01, InB is selected, etc.)
4. Hierarchically create a quad 4-to-1 mux using the symbolic version of your 4-to-1 mux. The inputs to the new mux should be four 4-bit busses labeled InA(3:0), InB(3:0), InC(3:0), and InD(3:0). The select bus is labeled S(1:0) and the output should be a bus labeled Out(3:0).
5. Test the mux you created and print out annotated results of your simulations. It is not necessary to exhaustively test all combinations of all 18 input pins, but choose patterns that make it obvious from the resulting trace file that the design is working. Handin the simulations.
6. Note: A testbench for Problem 1 is available here. However we recommend that you build your own testbench.

#### What to submit:

• For the written part: Printed annotated waveforms showing your unit works correctly. Label the inputs and output sequences explaining your verification. I don't expect you to turn in more than one or two pages. You should have one set of waveforms for the basic 2-to-1 mux and one for the final quad 4-to-1 mux.
• For electronic submission:
1. Submit all the verilog files. See instructions here
2. Make sure you run the verilog check on all the files. Not necessary to run it on your testbench.

Problem 2

1. Design a 1-bit full adder using only NOT, NAND, NOR, and XOR gates (again use the provided modules). Label the inputs as 'A', 'B' and 'Cin' (carry-in). Label the outputs as 'S' and 'Cout'.
2. Verify the correctness of the 1-bit adder over all combinations of inputs. Handin the simulations.
3. Using the 1-bit full adder you created above, design a ripple carry adder that adds two 4-bit binary numbers. Make the inputs and outputs are 4-bit busses labeled A(3:0), B(3:0), and SUM(3:0), respectively. Label the carry in CI and the carry out CO. Show the simulation results for 8 combinations of values of the two input numbers. Handin the simulations.
4. Using the 4-bit full adder you created above, design a ripple carry adder that adds two 16-bit binary numbers. Make the inputs and outputs are 16-bit busses labeled A(15:0), B(15:0), and SUM(15:0), respectively. Label the carry out from the adder CO. Show the results for 8 combinations of values of the two input numbers. Handin the simulations.
5. In one or two sentences, explain how your design might be simpler if you only needed to compute A+1 rather than A+B

#### What to submit:

• For the written part: Printed annotated waveforms showing your unit works correctly. Label the inputs and output sequences explaining your verification. I don't expect you to turn in more than one or two pages. You should have one set of waveforms for the basic 1 bit full-adder, one for the 4-bit adder, and finally one for the 16-bit adder. Obviously, you will not be able to exhaustively show waveforms for the 16-bit adder. Explain your testing strategies and describe a judicious subset of cases to show.
• For electronic submission:
1. Submit all the verilog files. See instructions here
2. Make sure you run the verilog check on all the files. Not necessary to run it on your testbench.

Problem 3

A sequence detector is a finite state machine that outputs "1" when a particular sequence is detected and outputs "0" otherwise. For example, a sequence detector designed to detect the sequence "1010" outputs "1" every time this sequence is seen in the input stream. Thus, for an input stream "101010" the output will be "000101".

Design a sequence detector that detects two specific digits represented in binary coded decimal(BCD). Your design should sample a one bit input 'InA' at the rising edge of a clock signal 'Clk'. Use the 'Reset' signal to initialize any registers you may use. Select the sequence to detect from the following table, using the least significant digit in your UW ID number. For example, if your id is 902 631 9385 , the least significant digit is 5, so you should select the sequence 85, which is 10000101 in BCD. The sequence detector should also detect overlapping sequences.

NOTE: You are expected to implement a Moore machine (and not a Mealy machine)

 Last digit Sequence 0 or 5 85 1 or 6 97 2 or 7 42 3 or 8 53 4 or 9 28

You should complete each of the following:

• Construct the state diagram of the machine. Turn in the state diagram.
• Implement the sequence detector using Verilog.
• Simulate your design using a testbench. You should chose an input sequence that shows that your detector works correctly. Be sure to turn in the annotated trace of your simulation and describe why the sequence shows that your detector works properly.

#### What to submit:

• For the written part: