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Consider the example single-error-correcting code with a minimum Hamming distance of three example in the ECC1 handout. The handout can be found at the bottom of this page
Multiply the following 2's complement 8-bit numbers using Booth's algorithm. Use this Booth algorithm handout for details. See LecturesAndHandouts page - go to the very end of the page and you will see called Booth recoding handout. This is the link. Verify your answer by computing A, B and the product in decimal.
Multiplicand A = 0010 1011 Multiplier B = 0101 0101
Divide the following positive numbers using the restoring division algorithm. Show all the steps as in Figure 3.11 on page 240 of the text book.
Verify your answer by converting A and B and your result (A / B) and remainder to decimal.
A = 0101 1000 B = 0101
This is a good reference on IEEE 754 standard; link
Write performance benchmarks to show off your processor. Done as a team.
These could measure different things like cache performance, forwarding, branch prediction etc. These programs should be relatively long first of all (100+ cycles or so), so that the warm-up effects of the pipeline get canceled out. Few examples:
I may use a subset of these to make final decision on what programs to use as the benchmark suite to decide the final best processor after the final demo. Each team must submit at least one program.
Virtual Memory: Consider a byte addressable system with 1GB physical memory and 4GB of virtual address space and no caching.
1) What should be the width of the address bus within the processor (prior to address translation)? What should be the width of the address bus after address translation?
2) Assume that the system uses 4KB pages. How many page table entries are required per process, (assuming that all processes uses all 4GB of the virtual address space)?
3) Now we are adding a TLB to speed up address translation. The TLB is fully associative with only four entries. The snapshot of the TLB and the contents of the relevant portion of the page table are shown below. Explain why the tags are 20 bits wide and why the physical page numbers are 18 bits wide.
Page table snapshot:
Consider the same system of Problem 6 and the snapshot of TLB and page tables for a given process.
1)Given that this process generates the following stream of virtual addresses:
Classify each access as TLB hit/Page table hit/Page fault.
2)For each memory access which is not a page fault, what is the translated physical address?
What are types of programs or problems that are not suitable for GPUs? Give one example. You may describe an algorithm, psuedo-code or c-code. Justify why you think that the performance of this algorithm will be bad on GPUs.
You have designed a single-issue in-order processor for the term project in this course. What are the main design principles/ideas that are added to a modern OOO processor compared to the processor you have built?
Do problems 7.7.1 and 7.7.2 in page 693 of textbook.
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