Main »

# Homework 6

Homework 6

Due 05/09
Weight: 15%

Use this cover-sheet as the first page of your homework. Download the word doc, fill your name and print. Or in hand write the details in big big letters. word doc, [pdf

### 1.  Submission

• For problem 5:
• Electronic submission: One per project team
• Written/Printed submission: To be done by each team member.
• All other problems:
• To be done individually (with individual submissions)

### 2.  Grading scheme (total : 100 points)

• Randomly chosen 5 problems (out of 12) to be graded.
• Each graded problem carries 20 points.

### 3.  Problem 1

Consider the example single-error-correcting code with a minimum Hamming distance of three example in the ECC1 handout. The handout can be found at the bottom of this page

1. Find the codewords for these datawords :
1. 00000111
2. 10001111
3. 11001010
4. 10101001
2. For this part assume that at most one bit can be in error. If the following values are read from the memory (stored using the above encoding in the order ` C3 C2 C1 C0 b7 b6 b5 b4 b3 b2 b1 b0`), find the correct dataword.
1. 0011 11111111
2. 0011 01111111
3. 1110 00011111
4. 0111 10001011

### 4.  Problem 2

Multiply the following 2's complement 8-bit numbers using Booth's algorithm. Use this Booth algorithm handout for details. See LecturesAndHandouts page - go to the very end of the page and you will see called Booth recoding handout. This is the link. Verify your answer by computing A, B and the product in decimal.

Multiplicand A = 0010 1011 Multiplier B = 0101 0101

### 5.  Problem 3

Divide the following positive numbers using the restoring division algorithm. Show all the steps as in Figure 3.11 on page 240 of the text book.

Verify your answer by converting A and B and your result (A / B) and remainder to decimal.

A = 0101 1000 B = 0101

### 6.  Problem 4

1. Show the IEEE 754 binary representation for the floating point number 17.384 (base 10)
2. Convert the following number given in IEEE 754 binary representation to the equivalent decimal number
`0000 0100 0000 0100 1001 0000 1001 0110`

This is a good reference on IEEE 754 standard; link

### 7.  Problem 5

Write performance benchmarks to show off your processor. Done as a team.

These could measure different things like cache performance, forwarding, branch prediction etc. These programs should be relatively long first of all (100+ cycles or so), so that the warm-up effects of the pipeline get canceled out. Few examples:

• Examples of common scenarios in a typical applications - for example: what happens typically in a photoshop image filter.
• Testing of worst-case branch prediction behavior

I may use a subset of these to make final decision on what programs to use as the benchmark suite to decide the final best processor after the final demo. Each team must submit at least one program.

What to submit:

On your printed homework, write a brief description of your program. And the number of cycles the program takes on your processor.

### 8.  Problem 6

Virtual Memory: Consider a byte addressable system with 1GB physical memory and 4GB of virtual address space and no caching.

1) What should be the width of the address bus within the processor (prior to address translation)? What should be the width of the address bus after address translation?

2) Assume that the system uses 4KB pages. How many page table entries are required per process, (assuming that all processes uses all 4GB of the virtual address space)?

3) Now we are adding a TLB to speed up address translation. The TLB is fully associative with only four entries. The snapshot of the TLB and the contents of the relevant portion of the page table are shown below. Explain why the tags are 20 bits wide and why the physical page numbers are 18 bits wide.

TLB snapshot:

 Valid Tag Physical page number 1 20'h0000B 18'h0000C 1 20'h00007 18'h00004 1 20'h00003 18'h00006 0 20'h00004 18'h00009

Page table snapshot:

 Valid Physical page or in disk 1 18'h00005 0 0 1 18'h00006 1 18'h00009 1 18'h0000B 0 1 18'h00004 0 0 1 18'h00003 1 18'h0000C

### 9.  Problem 7

Consider the same system of Problem 6 and the snapshot of TLB and page tables for a given process.

1)Given that this process generates the following stream of virtual addresses:

32'h0000_7000

32'h0000_B000

32'h0000_3000

32'h0000_BA5A

32'h0000_BFFF

32'h0000_AA5A

32'h0000_5FFF

32'h0000_1CCC

Classify each access as TLB hit/Page table hit/Page fault.

2)For each memory access which is not a page fault, what is the translated physical address?

### 10.  Problem 8

What are types of programs or problems that are not suitable for GPUs? Give one example. You may describe an algorithm, psuedo-code or c-code. Justify why you think that the performance of this algorithm will be bad on GPUs.

### 11.  Problem 9

You have designed a single-issue in-order processor for the term project in this course. What are the main design principles/ideas that are added to a modern OOO processor compared to the processor you have built?

### 12.  Problem 10

Do problems 7.7.1 and 7.7.2 in page 693 of textbook.