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Electronic submission instructions

Tasks

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For this course we will use dropbox at Learn@UW.

  • First login to Learn@UW, using your netid and password.
  • Locate the page for CS552.
  • Click on assignments tab, choose dropbox
  • Click on the appropriate folder for the evaluation component for which you want to make the submission.
  • Click on 'Add a file', in the new window, browse for the file and click 'Upload'.
  • Click the 'Submit' button.

Ignore everything below this green box. It is there for reference for the TAs and Instructor!

Homework 0

None

Homework 1

   1. Make a folder for each problem (hw1_1, hw1_2 and hw1_3).
   2. Each folder should contain all the verilog files for that problem. You don't have to turn in your testbench.
   3. name and signals for the top level module should be :
          problem1: quadmux4_1( InA, InB, InC, InD, S, Out);
          problem2: fulladder16( A, B, SUM, CO);
          problem3: seqdec_XX(InA, Clk, Reset, Out);
                           where XX is the sequence in hex that your module will detect (85, 97...).
   4. tar these 3 folders to <cs username>.tar [example : tar cvf ragh.tar hw1_1 hw1_2 hw1_3 ]
   5. Submit only the tar file

Homework 2

  1. Make a folder the first problem called hw2_1; and for the second problem called hw2_2
  2. Each folder must contain all the verilog files for the respective problem as well as outputs of running vcheck.sh. You may need to have copies of some files in each directory
  3. tar these two folders in a file called hw2.tar. [tar cvf hw2.tar hw2_1 hw2_2 ]
  4. Submit only the tar file

Homework 3

  1. Make a folder each verilog problem; For problem 1 name it hw3_1, for problem 2 - hw3_2 and for problem 3 - hw3_3
  2. Each folder must contain all the verilog files for the respective problem. You may need to have copies of some files in each directory
  3. Each folder should also contain .vcheck.out files for all verilog files in the folder.
  4. tar those three folders in a file called hw3.tar. [example : tar cvf hw3.tar hw3_1 hw3_2 hw3_3]
  5. Submit only the tar file

Homework 4

Problem 1, 2 & 3

  1. Make a folder for each verilog problem, For problem 1 name it hw4_1, for problem 2 - hw4_2 and for problem 3 - hw4_3
  2. Each folder must contain all the verilog files for the respective problem. You may need to have copies of some files in each directory.
  3. Problem 1 folder should also contain .vcheck.out files for all the verilog files in the folder.
  4. Problem 2 and 3 folders must contain all the verilog files, synthesised rf.syn.v, fifo.syn.v files and outputs for the respective problem. You may need to have copies of some files in each directory. In particular, the area_report.txt, timing_report.txt files must be present in this folder.
  5. tar all these folders of problem 1, 2, 3 into a file called hw4.tar [example : tar cvf hw4.tar hw4_1 hw4_2 hw4_3] and submit only this tar folder to the group dropbox submission.

Problem 12

  1. Make a folder called hw4_12
  2. The folder should contain all the .asm files for the instruction assigned to you.
  3. Each .asm file should be named with the following convention: <instruction_name>_X.asm, as specified in the hw4. [example: addi_6.asm]
  4. tar this folder of problem 12 into a file called hw4_12.tar [example : tar cvf hw4_12.tar hw4_12] and submit only this tar folder to the individual dropbox submission.

Homework 5

  • State machine for cache controller of problem 1 is due one week before (04/09) in class.
  • For problems 1 and 2, tar cvf hw5.tar hw5_1 hw5_2

the following directory structure - Each of hw5_1 and hw5_2 containing 4 of the following subdirectories. Submit this tar folder to the group submission dropbox.

  1. RTL:
    1. verilog files
  2. Vcheck:
    1. vcheck.out for all verilog files.
  3. Verification:
    1. Using mem_system_randbench testbench, the simulation log output, rename the file randbench.log.
    2. Using mem_system_perfbench testbench, all additional trace files your wrote (note that you should have at least 5 such files). Each such file should end with the extension .addr
  4. Synthesis
    1. mem_system.syn.v
    2. the 3 report files (area_report,timing_report,cell_report). Make sure the cell area is not zero.
  • Also, a physical copy of annotated waveforms should be submitted in class.

Homework 6

 For problem 5, tar cvf hw6.tar test1.asm test2.asm ....... README
  • test1.asm, test2.asm and so on: Note that you should write at least one test program (per team).
  • README : containing a brief description of all the tests in this directory. In particular, clearly mention what performance feature you intend to cover with each test program.

Demo1 / Demo2 / Final Demo

Submit a single tgz file : <username>.tgz with the following directories :

 * verilog/ containing all verilog files. Please copy over ALL necessary files, your processor should be able compile and run with files from this directory alone. 
 * verification/mytests/ The assembly (.asm) files that you have written.
 * verification/results/ A list of summary.log files output (including your testcases). 
 * synthesis/ the area and timing report.

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