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Course calendar and lecture notes

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1.  Lecture Schedule

This course's text readings will cover Chapters 1 through 7, Appendix A and Appendix C. The following subsections are omitted (interested students can skim over them):

  • 2.11, 2.15, 2.16, 2.17, 2.2.0
  • 3.6, 3.7, 3.10
  • 4.15
  • 5.8, 5.10
  • 6.5 through 6.14
  • 7.6 through 7.14
  • C.11 through C.13
Date Topic Reading Homework assigned
22-Jan Introduction Ch 1 HW0
24-Jan Instructions 1 Ch 2.1-2.8 HW1
29-Jan Instructions 2 Ch 2.10-2.14, 2.18-2.19
31-Jan Verilog Tutorial
5-Feb Arithmetic Ch 2.4, Ch 3.1-3.4
7-Feb Arithmetic 2 C.3-C.6 from appendix on CD HW2
12-Feb Performance Ch 1.4
14-Feb The processor: datapath Ch 4.1-4.3
19-Feb Control path Ch 4.4 HW3
21-Feb Pipelining 1 Ch 4.5
26-Feb Pipelining 2 Ch 4.6
28-Feb Pipelining 3 Ch 4.7
5-Mar Pipelining 4 Ch 4.8-4.11
7-Mar Miscellaneous HW4
12-Mar Mid term review
14-Mar Mid term 1
19-Mar Memory 1 Ch 5.1-5.2 HW5
21-Mar Memory 2 Ch 5.3
26-Mar Spring break
28-Mar Spring break
2-Apr Cache implementation Ch 5.7
4-Apr Memory 3 Ch 5.4-5.6
9-Apr Memory 4
11-Apr Storage Ch 6.1-6.6
16-Apr Error correction codes See ECC handout
18-Apr Advanced microprocessors (OOO) HW6
23-Apr Multiprocessors Ch 5.8 and Ch 7.1-7.5
25-Apr GPU Appendix A
30-Apr Arithmetic 3 Ch 3.3-3.5
2-May Arithmetic 4
7-May Future
9-May Final review
8-May Final demo
9-May Final Report
13-May Final Exam

2.  Lecture powerpoint slides

Lecture notes can be downloaded from a UW-madison computer (wisc.edu domain). If you trying to access from a machine off campus, use the common course login and password.

Lecture notes

Lecture notes (4 slides per page)

Course organization and logistics

4 on a page

Introduction

4 on a page

ISA

4 on a page

Control: Procedure calls

4 on a page

Arithmetic

4 on a page

Performance

4 on a page

Processor

4 on a page

Pipelining

4 on a page

Pipelining and misc.

4 on a page

Mid-term review

4 on a page

Mid-term review

4 on a page

Memory
Cache handout

4 on a page
Cache handout

IO

4 on a page

Arithmetic part b

4 on a page

3.  MIPS and C-Code examples - 01/29

4.  Verilog Tutorial Slides, 4 on a page - 01/31

5.  Example of well written verilog code - 01/31

dyser_stage.v - this is code from a design from my research group. Notice a few things in that well written example code.

  • Parameters have been separated out into a separate file called dyser_config.v
  • Clean separation of the sequential elements and logic
  • Well written case statements
  • And some syntactic things: each input, output, wire, and reg is declared on a separate line
  • The module itself is simple and small. Hence easy to design, implement and verify. To build complex design, hierarchy is the key.

6.  Verilog cheat sheet - 02/10

Verilog cheat sheet pdf, Verilog cheat sheet word doc version if you want to edit,

7.  Other handouts and reference


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