Main »

Project Modules Provided


edit SideBar

You may use the the following pre-built Verilog modules in your project. These do not follow the Verilog rule, so do not run Vcheck on them.

  • Processor hier top level with clock generator. You MUST use ONLY this top. NO modifications allowed. proc_hier.v verilog source code. Modified January 17, 2013
  • Your processor top-level module must be called proc and must be in a file called proc.v. You MUST modify this file and instantiate sub-modules and such inside it. proc.v verilog source code. Modified January 17, 2013
  • Processor top level testbench. You MUST use this test bench. You may make modifications if necessary. proc_hier_bench.v verilog source code. Modified January 17, 2013
    • For the demos and before final submission you MUST edit lines 57 to 65 and make those wire assignments.
    • As you can see this testbench prints a log of all writes to the register file, reads from data memory, and writes to data memory.

  • Processor top level testbench for pipelined processor.
    proc_hier_pbench.v verilog source code. Modified 04/10.
    You must run with the -pipe option
    Modified 05/03 and added support for DHIT_RATE and IHIT_RATE

Page last modified on January 17, 2013, visited 5496 times

Edit - History - Print - Recent Changes (All) - Search