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Suggested Project Stages and Implementation
These stages are not necessarily broken into equal weight; some may take considerably longer than others.
The overall implementation and verification plan for the project is the following:
To start, you should do a single-cycle, non-pipelined implementation. Figure 4.24 on page 329 is a good place to start.
For this stage, use the Single cycle perfect memory. Since you will need to fetch instructions as well as read or write data in the cycle, use two memories -- one for instruction memory and one for data.
After you have completed the single cycle implementation, you will next implement a pipelined version of the architecture. A good starting point is Figure 4.65 on page 384 of COD fourth edition. Continue to use the single cycle memory.
Be sure that the non-pipelined version is functional before you try the pipelined version. While designing the non-pipelined version, make considerations that will allow easy conversion to the pipelined version.
The next few steps will improve our memory and make it more realistic.
At this step, replace the original single-cycle memory with the Aligned single cycle memory. This is a very similar module, but it has an "err" output that is generated on unaligned memory accesses. Your processor should halt when an error occurs. Verify your design.
At this step, replace the single cycle memory with the Stalling memory. This is a very similar module, but has stall and done signals similar to the cache you built. Your pipeline will need to stall to handle these conditions. Verify your design.
The simple memory module is still highly idealized. Real memory systems are pipelined and use multiple banks. You are provided with such a simple four-banked memory module that models a simple DRAM controller.
I suggest that you do not interface this four-banked memory directly to your processor. Just use it to fetch blocks for your cache. This sub-step does not require verification. Make sure your design continues to compile. Proceed to stage 4.
Replace your memory modules with the cache modules. This module has a "stall" output, which takes the place of the "ready" output of the stalling memory. Here, however, you will need to implement a state machine to handle cache misses. Upon a miss, the previous contents of the cache line will need to be written back to memory if dirty, and the new line will need to be loaded into cache. The main memory will take multiple cycles to perform each access.
Again, follow an incremental approach like we did for the stalling memory.
Add a second cache module alongside each of your existing cache modules, and implement a two-way set-associative memory. Use the 2-way set associative cache developed in homework 5.
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