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Submission checklist


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Make sure you have done the following:

  1. Use this cover-sheet as the first page of your homework for written part. Download the word doc, fill your name and print. Or in hand write the details in big big letters. word doc, [pdf
  2. Each Problems X has its own folder.
  3. Everything required to run problem X should be in X's folder.
  4. Every verilog file must contain exactly 1 module, which must have the same name as the file. Run name-convention-check script on the directory.
  5. There must also not be any illegal verilog commands.
  6. For HW1, turn in only the design files (Do not turn in testbench files)
  7. For HW2-HW6 and for the project demos, turn in all verilog files including the testbench files.
    1. Note: include the provided *_hier.v file (Without any modifications)
    2. Note: include a *_hier_bench.v file which instantiates *_hier.v
  8. Run vcheck on all you design files (exclude testbench files *_hier.v and *_hier_bench.v) and turn in .vcheck.out files.

Page last modified on February 15, 2013, visited 1303 times

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