`include "dyser_config.v" // dff_rn is a d-flip-flop with negative reset // dff_rne is a d-flip-flop with negative reset and enable module stage( /* inputs */ ready_in, valid_in, credit_in, data_in, clk, rst_n, /* outputs */ credit_out, data_out, valid_out, ready_out ); parameter ID = 0; parameter EDGE = 0; input ready_in; input valid_in; input credit_in; input [`DATA_WIDTH:0] data_in; input clk; input rst_n; output credit_out; output [`DATA_WIDTH:0] data_out; output valid_out; output ready_out; /////////////////////////////////////////////////// // // wires // ////////////////////////////////////////////////// reg credit_out; reg data_en; reg [`DATA_WIDTH:0] data; reg valid; reg ready_out; reg state; ////////////////////////////////////////////////////// // // states: CN: has credit NR: has ready data // ////////////////////////////////////////////////////// parameter CN = 1'b0; parameter NR = 1'b1; // state + next state logic wire next_state; dff_rn state_ff( .din(next_state) .q(state) .rst_n(rst_n) ); assign next_state = (state == CN) ? ready_in ? NR : CN : /*state == NR*/ credit_in ? CN : NR; // output logic (Mealy) always @(state or credit_in or ready_in) //always @(*) case ({state,credit_in,ready_in}) //for state CN 3'b0_0_0: begin ready_out = 1'b0; data_en = 1'b0; credit_out = 1'b1; end 3'b0_0_1: begin ready_out = 1'b0; data_en = 1'b1; credit_out = 1'b1; end 3'b0_1_0: begin ready_out = 1'b0; data_en = 1'b0; credit_out = 1'b1; end 3'b0_1_1: begin ready_out = 1'b0; data_en = 1'b1; credit_out = 1'b1; end //for state NR 3'b0_0_0: begin ready_out = 1'b1; data_en = 1'b0; credit_out = 1'b0; end 3'b0_0_1: begin ready_out = 1'b1; data_en = 1'b0; credit_out = 1'b0; end 3'b0_1_0: begin ready_out = 1'b1; data_en = 1'b0; credit_out = 1'b0; end 3'b0_1_1: begin ready_out = 1'b1; data_en = 1'b0; credit_out = 1'b0; end default: begin //$display("output logic ERROR time: %d", $time ); ready_out = 1'b0; data_en = 1'b0; credit_out = 1'b0; end endcase // data and valid FF dff_rne_data_width data_ff( .din(data_in) .q(data) .en(data_en) .rst_n(rst_n)); dff_rne valid_ff( .din(valid_in) .q(valid) .en(data_en) .rst_n(rst_n)); assign data_out = data; assign valid_out = valid; endmodule