|CS552 Course Wiki: Spring 2016||Main »
552 Bug Hall Of Fame
On this page... (hide)
--- Bug report 1 Shan-Hsiang Shen
Hello Professor Sankaralingam:
When I test my cache design with mem_system_randbench.v, I encounter the following error
LOG: REQ 516 Cycle 5651 Rd Addr 0xa9e8 Value 0x2axx ValueRef 0x0000
However, Addr 0xa9e8 is never written before request 516.
In memory4c.v each memory write or read will be done by access mem[addr_1c<<1],
but addr_1c is only 12 bits which is the same as the bit number of input addr. Therefore, addr_1c <<1 will miss the highest bit of input addr.
a9e8 and 29e8 will access the same memory location. Is this a problem with memory4c.v?
I have try to change addr_1c from 12 bits to 13 bits, and than I can pass the test of mem_system_randbench.
Thank you very much.
--- Bug report 2 Vaishali Karanth
I see that in memory4c.v, input address is shifted left before indexing into memory array. I believe it is done for alignment purpose.
Because of the shifting MSB of the address is lost, the addresses which differ only by MSB bit will point to the same location(if both addresses belong to same bank). For example, both 0xe000 and 0x6000 are treated as 1100 0000 0000 0.
I have a case where some value say 0x1234 is written into 0xe0e8, and later in time I read 0x60e8(this location was not written before) and it returns 0x1234 instead of 0!
Simulation fails only for above type of addresses for me, so I doubt it could be an issue with memory4c.v. Please correct me if my understanding of memory4c.v is wrong.
|Page last modified on January 16, 2009, visited 2331 times|