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Date Topic Reading Homework assigned Homework due Solutions Project
19-Jan Introduction Ch 1 HW0 HW0
21-Jan Instructions 1 Ch 2.1 - 2.15 HW1 SOLN-HW1
26-Jan Instructions 2 (slides above) Skim Ch 2.17 and 2.18
28-Jan Verilog Tutorial See slides and cheat sheet
2-Feb Verilog Tutorial (slides above) See slides and cheat sheet
4-Feb Arithmetic (Design) Ch 3 and Appendix B.1-B.6 HW2 HW1 SOLN-HW2 Form project team (Feb 8th)
9-Feb Arithmetic (Implementation) Ch 3 and Appendix B.1-B.6
11-Feb Processor (datapath) Ch 4.1 - 4.10
16-Feb Processor (Control path) Ch 4.1 - 4.10 HW3 HW2 SOLN-HW3
18-Feb Processor (Pipelining 1) Ch 4.1 - 4.10
23-Feb Processor (Pipelining 2) Ch 4.1 - 4.10 Project plan
25-Feb Processor (Pipelining 3) Skim 4.11 and 4.12
1-Mar Performance analysis Ch 1.6 - 1.10
3-Mar Miscellaneous HW4 HW3 SOLN-HW4 Design Review
8-Mar Mid term review
10-Mar Mid term 1
15-Mar Memory 1 Ch 5.1-5.2 HW5 HW4 SOLN-HW5
17-Mar Memory 2 Ch 5.3 Demo 1
22-Mar Spring break
24-Mar Spring break
29-Mar Memory 3 Ch 5.9
31-Mar Memory 4 CH 5.4-5.8
5-Apr Memory 5 CH 5.4-5.8
7-Apr No class review ch 5.8
12-Apr Storage Ch 5.11 Demo 2
14-Apr Error correction codes See ECC handout HW6 HW5 SOLN-HW6 Cache FSM turnin
19-Apr Multiprocessors 1 Ch 6.1-6.3
21-Apr Multiprocessors 2 Ch 6.4-6.5 Cache Demo
26-Apr GPU Ch 6.6
28-Apr OOO (1) no reading
3-May OOO (2) no reading
5-May Final review HW6
9-May Final demo Final demo
10-May Final Report Final report
12-May Final Exam

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