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  1.   1.  Summary
  2.   2.  Syntax for running the script.
  3.   3.  Additional flags
    1.   3.1  -wave
    2.   3.2  -prog
    3.   3.3  -list
    4.   3.4  -pipe
    5.   3.5  -addr
    6.   3.6  -brief
  4.   4.  Simulating full programs on your processor
  5.   5.  Testing different sub-units of your design
  6.   6.  Add Comments

1.  Summary

Instead of using Modelsim's builtin GUI for compilation and simulation you can use a simulation script called to simulate your verilog design. This script can be used only if your verification is done using a verilog test bench.

  • Add the following to your path variable: /u/k/a/karu/public/html/courses/cs552/spring2013/handouts/bins
  • Identify the verilog files that you want to test, lets call them foo0.v, foo1.v, and foo2.v.
  • Call your testbench foo_bench.v
  • Your testbench must be written so that it will stop automatically after running for some cycles by calling $finish .
  • The script will simulate your testbench and track the waveform output in a file called dump.vcd and dump.wlf. The text output of your testbench will be written to a file called transcript.
  • You must instantiate the clkrst.v module in your design if you want to use this script. If you are testing pure combinational logic, simply instantiate the clkrst module in your testbench as a dummy module.
  • If you use this script, you can simply edit your verilog using your favorite editor, and compile and simulate using the script, using Modelsim only as a waveform viewer.

2.  Syntax for running the script.

At the unix prompt:

prompt% <name of your testbench module> <testbench file name> <list of verilog files> 

All the verilog files that your design uses must be specified on the command line. For our example, let's assume the module in the testbench is called foo_bench. Then you should execute:

prompt% foo_bench foo_bench.v foo0.v foo1.v foo2.v

Note: foo_bench is specified once, and foo_bench.v is specified once. The first argument specifies the module name, the second specifies the verilog filename.

If you used the rf_bench.v from homework 3 as the testbench for example, you would issue the command:

prompt% rf_bench rf_bench.v clkrst.v dff.v rf.v rf_bench.v rf_hier.v

Convert the $stop to $finish in the testbench to get this script to work with that testbench. You will then see output that looks like the following:

Compiling the following files: clkrst.v dff.v rf.v rf_bench.v rf_hier.v 
Top module: rf_bench
** Warning: (vlib-34) Library already exists at "__work".
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module clkrst
-- Compiling module dff
-- Compiling module rf
-- Compiling module rf_bench
-- Compiling module rf_hier

Top level modules:
Reading /afs/ 

# 5.8b

# vsim -lib __work -c rf_bench 
# //  ModelSim SE 5.8b Jan 01 2004 Linux 2.6.9-55.0.12.EL
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //
# Loading __work.rf_bench
# Loading __work.rf_hier
# Loading __work.clkrst
# Loading __work.rf
VSIM 1> run -all

*** Your testbench simulation starts here ****

# ** Note: $finish    : rf_bench.v(100)
#    Time: 100010 ns  Iteration: 0  Instance: /rf_bench
Verilog simulation successful
Created a dump file dump.wlf. Open in vsim

You can now view a waveform of the simulation by issuing the following on the command-line:

prompt% vsim -view dataset=dump.wlf

You can now view all waveforms of all the signals in your design. The waveforms are saved to a file called dump.vcd and dump.wlf. In Model-sim, you will see a tab showing dataset. Click on the Edit menu and choose Wave. You can drag and drop modules into the waveform window to look at different signals as before.

If you make any changes to any of the verilog files, simply reissue the command again:

prompt% foo_bench foo_bench.v foo0.v foo1.v foo2.v

And re-open vsim.

You can specify wildcards like *.v to compile all the .v files. module_name *.v

3.  Additional flags

3.1  -wave -wave

Will automatically start vsim with the waveform viewer after simulating your design.

3.2  -prog -prog <assembly filename> proc_hier_bench *.v

Assemble the assembly file and run it on the processor.

3.3  -list -list <filename with list of assembly files> proc_hier_bench *.v

Example list file foo.list which contains one assembly file on each line.


Run the programs one after another on the processor. Results written to a file called summary.log.

3.4  -pipe

This option should be used for simulating a pipelined processor (For demo2 onwards).

3.5  -addr -addr <address trace filename> mem_system_perfbench *.v

This option is similar to -prog. It is used to specify an address trace to be used for HW5's mem_system_perfbench testbench. This option does not make sense for any other testbench.

3.6  -brief

Show less output on screen, record to wsrun.log

4.  Simulating full programs on your processor

The script has a -prog switch using which you can specify a program to simulate on your processor. The script will automatically assemble it, copy over the loadfile and compile and simulate your processor and run that program by loading into memory.

For example:

prompt% -prog 
proc_hier_bench *.v

The above command will run the easyTest program in your processor.

5.  Testing different sub-units of your design

Use the script to simulate and verify individual units rapidly, each with its own testbench as you build up your processor. This script gets rid of the need to create project files and using the GUI to compile and run the simulation. The script takes care of everything and we use ModelSim only as a waveform viewer for debugging.

You will find this script to be useful as we transition to more complex designs.

6.  Add Comments


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anonymous?31 October 2012, 13:01

yet another test comment

anonymous?20 February 2009, 11:36

another test comment

foobar?20 February 2009, 11:34


karu?20 February 2009, 11:33

test comment

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