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Homework 1

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Due 02/04 at 1:00PM
Weight: 20% (tentative)

I highly recommend getting started early!

The main objective of this problem set is to become familiar with the ModelSim program and the CS workstations. Before starting this homework you should do the following:

  1. Follow the instructions on Getting started with Mentor to get your environment setup.
  2. Read the Command-line Verilog Simulation Tutorial. Additional references are in the Tools page.
  3. Read the Verilog Cheat sheet Verilog cheat. Everything you need to know about Verilog is in this document.
  4. Read the Verilog file naming conventions pages and adhere to those conventions.
  5. See Handin Instructions before getting started with homework.

You should simulate your solutions both to verify the correct function of your designs for yourself. You also have to hand in a copy of the verilog files.

This assignment will take a significant amount of time if you are not already familiar with ModelSim and hardware design languages. Get started as soon as possible. In the 2nd week of class, there will be a lecture on Verilog.

To deal with complexity, use a "divide and conquer" or hierarchical design approach. Divide the circuit into logical pieces, called blocks, which can be composed to form the larger circuit. For example, a 4-to-1 multiplexor or mux can be composed from 2-to-1 muxes. Hierarchical design reduces both the complexity faced by the designer and the complexity of the computer's representation of the schematic. While hierarchical design may seem unnecessary for something as simple as a 4-to-1 mux, remember that modern computers have millions of gates.

Problem 1

  1. Design a 1-bit 2-to-1 multiplexer using only NAND, NOR, and NOT gates. Implement the circuit in verilog using these modules. These modules can be found in the Homework Modules Provided page. Note that your implementation will be different than the one presented in the ModelSim Tutorial, because of the restrictions. The input data lines of the multiplexer should be labeled InA and InB, the select line labeled S, and the output labeled Out.
  2. Simulate the multiplexer over all possible combinations of inputs. You can do this by applying clocks of different periods to each input and then running the simulation long enough for all combinations to appear.
  3. Use the 2-to-1 mux you designed in step 1 to hierarchically create a 4-to-1 mux. Label the inputs InA, InB, InC, and InD, and the output Out. Make your select input a bus (not single wires); name it S(1:0) (If S is 00, InA is selected; if S is 01, InB is selected, etc.)
  4. Hierarchically create a quad 4-to-1 mux using the symbolic version of your 4-to-1 mux. The inputs to the new mux should be four 4-bit busses labeled InA(3:0), InB(3:0), InC(3:0), and InD(3:0). The select bus is labeled S(1:0) and the output should be a bus labeled Out(3:0).
  5. Test the mux you created. It is not necessary to exhaustively test all combinations of all 18 input pins, but choose patterns that make it obvious that the design is working.
  6. Use the testbench provided for testing.

What to submit:

  • For electronic submission:
    1. Submit all the verilog files. See instructions here
    2. Make sure you run the verilog check on all the files. Not necessary to run it on your testbench.

Problem 2

  1. Design a 1-bit full adder using only NOT, NAND, NOR, and XOR gates (again use the provided modules). Label the inputs as 'A', 'B' and 'Cin' (carry-in). Label the outputs as 'S' and 'Cout'.
  2. Verify the correctness of the 1-bit adder over all combinations of inputs.
  3. Using the 1-bit full adder you created above, design a ripple carry adder that adds two 4-bit binary numbers. Make the inputs and outputs are 4-bit busses labeled A(3:0), B(3:0), and SUM(3:0), respectively. Label the carry in CI and the carry out CO.
  4. Using the 4-bit full adder you created above, design a ripple carry adder that adds two 16-bit binary numbers. Make the inputs and outputs are 16-bit busses labeled A(15:0), B(15:0), and SUM(15:0), respectively. Label the carry out from the adder CO.
  5. Think about how your design might be simpler if you only needed to compute A+1 rather than A+B. NO submission necessary for this.
  6. Use the testbench provided for testing.

What to submit:

  • For electronic submission:
  1. Submit all the verilog files. See instructions here
  2. Make sure you run the verilog check on all the files. Not necessary to run it on your testbench.

Problem 3

A sequence detector is a finite state machine that outputs "1" when a particular sequence is detected and outputs "0" otherwise. For example, a sequence detector designed to detect the sequence "1010" outputs "1" every time this sequence is seen in the input stream. Thus, for an input stream "101010" the output will be "000101".

Design a sequence detector that detects two specific digits represented in binary coded decimal(BCD). Your design should sample a one bit input 'InA' at the rising edge of a clock signal 'Clk'. Use the 'Reset' signal to initialize any registers you may use. Select the sequence to detect from the following table, using the least significant digit in your UW ID number. For example, if your id is 902 631 9385 , the least significant digit is 5, so you should select the sequence 85, which is 10000101 in BCD. The sequence detector should also detect overlapping sequences.

NOTE: You are expected to implement a Moore machine (and not a Mealy machine)

Last digitSequence
0 or 585
1 or 697
2 or 742
3 or 853
4 or 928

You should complete each of the following:

  • Construct the state diagram of the machine - make sure your draw this on paper. Even though we are NOT going to require you turn it in.
  • Implement the sequence detector using Verilog.
  • Simulate your design using a modified version of the testbench based on the examples provided. You should chose an input sequence that shows that your detector works correctly.
  • Please make a note of your ID number.

What to submit:

  • For electronic submission:
  1. Submit all the verilog files. See instructions here
  2. Make sure you run the verilog check on all the files. Not necessary to run it on your testbench.

Design note: You may find that your designs for these problems can produce "glitches" -- short pulses on a wire when no transition was expected. This is OK as long as the signal quickly returns to its correct value and no glitch can be clocked into a latch. You may be tempted to add additional do-nothing gates in order to delay some signals to get rid of the glitch. This is not necessary in general computer design. If you are called upon to produce a truly glitch-free design, e.g. for an asynchronous "ready" strobe or for clock gating, more rigorous techniques are needed anyway.



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