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Homework 2

Due 02/19
Weight: 20%

Use this cover-sheet as the first page of your homework. Download the word doc, fill your name and print. Or in hand write the details in big big letters. word doc, [pdf

Problem 1 and 2 alone can be done with your project partner. (Form teams by 8th February). Email me and the TA the group members and a unique team name. Your email should have the subject line: CS552 group creation. Also, update the course wiki's Project Teams page.

Submission:

  • Problems 1 & 2:
    • Written/printed submission: Individual submission by each project partner.
    • Electronic submission of verilog files: One submission per project team.
  • Problems 3 - 14:
    • Individual submission by each team member. (These problems should be done individually and not with your partner)

Important

1.  Problem 1

Design a 16-bit barrel shifter with the following interface. Consult lecture notes for barrel shifter design.

Inputs:

  • [15:0]In - 16 bit input operand value to be shifted
  • [3:0]Cnt - 4 bit amount to shift (number of bit positions to shift)
  • [1:0]Op - shift type, see encoding in table below

Output:

  • [15:0]Out - 16 bit output operand
OpcodeOperation
00rotate left
01shift left
10shift right arithmetic
11shift right logical

You should use Verilog to do this homework.

  • Use this file for the verilog module definition: shifter.v
  • Use the module shifter_hier in shifter_hier.v to instantiate the module shifter and the clkrst module. [Do not edit this file in any way]
  • You should also submit your testbench shifter_hier_bench.v which instantiates the module shifter_hier.

Before starting to write any verilog, I suggest the following:

  1. Break down your design into sub-modules.
  2. Define interfaces between these modules
  3. Draw paper and pencil schematics for these modules
  4. Then start writing verilog

Verify the design using representative inputs.

What to submit:

  1. Turn in neatly and legibly drawn schematics of your design.
  2. Annotated simulation trace of the complete design. Pick representative cases for your simulation input to turn in.
  3. Explain your choice of inputs and why they are representative.
  4. Electronically submit your verilog source code.
  5. Vcheck output must also be submitted. Run vcheck.sh or vcheck-all.sh.

1.1  Electronic submission instructions

See HandinInstructions page.


2.  Problem 2

This problem should also be done in Verilog. Design a simple 16-bit ALU. Operations to be performed are 2's Complement ADD, bitwise-OR, bitwise-XOR, bitwise-AND, and the shift unit from problem 1. In addition, it must have the ability to invert either of its data inputs before performing the operation and have a C0 input (to enable subtraction). Another input line also determines whether the arithmetic to be performed is signed or unsigned . Use a carry look-ahead adder (CLA) in your design. (Hint: First design a 4-bit CLA. Then use blocks of this CLA for designing the 16-bit CLA.) For all the shift and rotate operations, assume the number to shift is input A to ALU and the shift/rotate amount is bits [3:0] of input B.

OpcodeFunctionResult
000rllrotate left
001sllshift left
010srashift right arithmetic
011srlshift right logical
100ADDA+B
101ORA OR B
110XORA XOR B
111ANDA AND B

The external interface of the ALU should be:

Inputs

  • A[15:0], B[15:0] - Data input lines A and B (16 bits each.)
  • Cin - A carry-in for the LSB of the adder.
  • Op(2:0) - The OP code (3 bits.) The OP code determines the operation to be performed. The opcodes are shown in the Table above.
  • invA - An invert-A input (active high) that causes the A input to be inverted before the operation is performed.
  • invB - An invert-B input (active high) that causes the B input to be inverted before the operation is performed.
  • sign - A signed-or-unsigned input (active high for signed) that indicates whether signed or unsigned arithmetic to be performed for ADD function on the data lines. (This affects the Ofl output.)

Outputs

  • Out(15:0) - Data out (16 bits.)
  • Ofl - (1 bit) This indicates high if an overflow occurred.
  • Zero - (1 bit) This indicates that the result is exactly zero.

Other assumptions:

  • You can assume 2's complement numbers.
  • In case of logic functions, Ofl is not asserted (i.e. kept logic low).
  • Use this file for the verilog module definition: alu.v
  • Use the module alu_hier in alu_hier.v to instantiate the module alu and the clkrst module. [Do not edit this file in any way]
  • You should also submit your testbench alu_hier_bench.v which instantiates the module alu_hier.

Use hierarchical design and simulate each block by itself before you try the complete design. You must reuse the shift unit designed in Problem 1.

What to submit:

  1. Neatly and legibly drawn schematics, hand-drawn is fine
  2. Annotated simulation trace output of the complete design. Pick representative cases for your simulation input.
  3. You should explain why your inputs are representative.
  4. Electronically submit your verilog source code.
  5. Vcheck output must also be submitted. Run vcheck.sh or vcheck-all.sh.

2.1  Electronic submission instructions

See HandinInstructions page.


3.  Problem 3

Do problems 1.3.1 to 1.3.3 in page 59 of textbook.


4.  Problem 4

Do problems 1.4.1 to 1.4.3 in page 60 of textbook.


5.  Problem 5

Do problems 1.4.4 to 1.4.6 in page 61 of textbook.


6.  Problem 6

Do problems 1.6.1 to 1.6.3 in page 62 of textbook.


7.  Problem 7

Do only part a) of problems 1.10.1 to 1.10.3 in page 66 of textbook.


8.  Problem 8

Do problems 2.10.1 to 2.10.3 in page 188 of textbook.


9.  Problem 9

Translate the following code from C into MIPS instructions. Assume that the variables p, q, r, and s are defined as 32-bit integers in a C program.


   p = q - r;
   s = p + r;
   q = p - s;

Assume p is stored in $t1, q is stored in $t2, r is in $t3, and s is in $t4.


10.  Problem 10

Do problems 2.13.1 to 2.13.3 in page 190 of textbook.

Note: for 2.13.1, use the following instruction sequence instead of the sequence in the textbook:

sll $t2, $t0, 4

or $t2, $t2, $t1


11.  Problem 11

Do only part b) of problems 2.14.1 to 2.14.3 in page 191 of textbook. The question in the text book has some ambiguity. See clarifications below

For register $t0, here are the bit fields:

0 to j-1          [j bits]
j to i-1          [i-j bits]
i to 31           [32-i bits] (The diagram in the textbook marks this field as 31-i bits wide. This is wrong. This field is 32-i bits wide)

For register $t1, here are the bit fields:

0 to 13           [14 bits]
14 to 13+i-j      [i-j bits]
14+i-j to 31      [18+j-i bits]

12.  Problem 12

Implement the following C code in MIPS:

   for (i=10; i != 0; i--) {
       a[4 * i] = b[2 * i] + i;
   }

Assume that the base address of a[] is stored in $a0, and the base address of b[] is stored in $a1. Also, a and b are integer arrays.


13.  Problem 13

Do problems 2.39.1 to 2.39.3 in page 217 of textbook.



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