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Course calendar and lecture notes

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1.  Lecture Schedule

This course's text readings will cover Chapters 1 through 5, Appendix A, B, and Appendix C. The list of subsections omitted will be updated below (interested students can skim over them).

  • 2.16 through 2.18
  • 4.11, 4.12
  • 5.13
Date Topic Reading Homework assigned
19-Jan Introduction Ch 1 HW0
21-Jan Instructions 1 Ch 2.1 - 2.15 HW1
26-Jan Instructions 2 (slides above) Skim Ch 2.17 and 2.18
28-Jan Verilog Tutorial See slides and cheat sheet
2-Feb Verilog Tutorial (slides above) See slides and cheat sheet
4-Feb Arithmetic (Design) Ch 3 and Appendix B.1-B.6 HW2
9-Feb Arithmetic (Implementation) Ch 3 and Appendix B.1-B.6
11-Feb Processor (datapath) Ch 4.1 - 4.10
16-Feb Processor (Control path) Ch 4.1 - 4.10 HW3
18-Feb Processor (Pipelining 1) Ch 4.1 - 4.10
23-Feb Processor (Pipelining 2) Ch 4.1 - 4.10
25-Feb Processor (Pipelining 3) Skim 4.11 and 4.12
1-Mar Performance analysis Ch 1.6 - 1.10
3-Mar Miscellaneous HW4
8-Mar Mid term review
10-Mar Mid term 1
15-Mar Memory 1 Ch 5.1-5.2 HW5
17-Mar Memory 2 Ch 5.3
22-Mar Spring break
24-Mar Spring break
29-Mar Memory 3 Ch 5.9
31-Mar Memory 4 CH 5.4-5.8
5-Apr Memory 5 CH 5.4-5.8
7-Apr No class review ch 5.8
12-Apr Storage Ch 5.11
14-Apr Error correction codes See ECC handout HW6
19-Apr Multiprocessors 1 Ch 6.1-6.3
21-Apr Multiprocessors 2 Ch 6.4-6.5
26-Apr GPU Ch 6.6
28-Apr OOO (1) no reading
3-May OOO (2) no reading
5-May Final review
9-May Final demo
10-May Final Report
12-May Final Exam

2.  Lecture powerpoint slides

Lecture notes can be downloaded from a UW-madison computer (wisc.edu domain). If you trying to access from a machine off campus, use the common course login and password.

Lecture notes

Course organization and logistics

ISA

Arithmetic 1, Arithmetic 2

Performance

3.  Verilog Tutorial Slides, 01/28

4.  Example of well written verilog code

dyser_stage.v - this is code from a design from my research group. Notice a few things in that well written example code.

  • Parameters have been separated out into a separate file called dyser_config.v
  • Clean separation of the sequential elements and logic
  • Well written case statements
  • And some syntactic things: each input, output, wire, and reg is declared on a separate line
  • The module itself is simple and small. Hence easy to design, implement and verify. To build complex design, hierarchy is the key.

5.  Verilog cheat sheet - 02/10

Verilog cheat sheet pdf, Verilog cheat sheet word doc version if you want to edit,

6.  Other handouts and reference


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