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Recommended Hierarchy and Filenaming conventions


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Enforced rule for all verilog submissions

  • Every verilog file must define EXACTLY one module. If you define multiple modules in a verilog file, it will be considered a violation of cs552 verilog rules.
  • If a verilog file is called xor15.v, the module it contains must be named xor15.v
    • The filename and module name must have an EXACT one-to-one match
    • YOU CANNOT have a file called 15xor.v and in it create a module called adder.v
  • Run the name-convention-check script
  • Any instantiation of a module must include port names along with net-names.i.e
         clkrst c0(clk, rst) is NOT OK
         clkrst c0(.clk(clk), .rst(rst)) is CORRECT

Recommended Hierarchy and Filenaming conventions (For HW2-HW6 and project demos)

  • For example, your top-level module must be called foo_hier.v
  • It MUST contain clkrst.v
  • Its interface (input/output ports) should be identical to what is suggested in your homework problems
  • Name the module you are designing foo and instantiate foo inside foo_hier.v
  • See example rf_hier.v and rf.v for examples for the register file.
  • You will follow a similar convention for your project.
  • Create cpu.v and cpu_hier.v
  • Name all testbenches with the _bench suffix

For project.

We will follow this same convention for your project.

  • Your top most level with just the processor MUST be called proc.v. A template for this is already provided. See Project modules provided page.
  • You must use the provided proc_hier.v which will instantiate the clock generator and your processor. See Project modules provided page.
  • You must use the proc_hier_bench.v testbench. If you cannot absolutely use this, email the instructor and TA to find a solution. See Project modules provided page.

Page last modified on February 05, 2013, visited times

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