/* $Author: karu $ */ /* $LastChangedDate: 2009-03-06 00:27:19 -0600 (Fri, 06 Mar 2009) $ */ /* $Rev: 50 $ */ This register file testbench can be used to test a verilog module which implements a register file with the following interface: module rf_hier(/*AUTOARG*/ // Outputs read1data, read2data, // Inputs read1regsel, read2regsel, writeregsel, writedata, write ); input [2:0] read1regsel; input [2:0] read2regsel; input [2:0] writeregsel; input [15:0] writedata; input write; output [15:0] read1data; output [15:0] read2data; endmodule To use this testbench with wsrun.pl: 1) Copy rf_bypass_bench.v into the same directory as your other verilog files. hw4/problem3 2) At the prompt. prompt> wsrun.pl rf_bypass_bench *.v 3) You should the simulation run 4) If the testbench shows any errors, then you can open waveforms by executing this command. prompt> vsim -view dataset=dump.wlf 5) Fix any bugs, go to step 2. To use this testbench with ModelSim GUI: 1) Add all your verilog files that implement your register file to your project. You must have a rf_hier.v. Or download the following example files: http://www.cs.wisc.edu/~karu/courses/cs552/spring2009/handouts/verilog_code/hw3-rf/rf_hier.v http://www.cs.wisc.edu/~karu/courses/cs552/spring2009/handouts/verilog_code/hw3-rf/rf.v http://www.cs.wisc.edu/~karu/courses/cs552/spring2009/handouts/verilog_code/hw3-rf/clkrst.v 2) Add this file (rf_bypass_bench.v) to the project. 3) Click Compile->Compile All 4) Click the Library tab and expand the work library or whatever library name you provided while creating the project 5) Right-click on rf_bypass_bench.v and choose simulate 6) On the right-hand window pane, you will now see a vsim prompt. 7) At that vsim prompt, type: run -All 8) Voila, the simulation will run for 1000 "cycles" 9) Use the waveform viewer to look at signals and such 10) To rerun, the simulation, you must first reset the simulator. You can do this by typing this at the vsim prompt: restart // DUMMY LINE FOR REV CONTROL :5: