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Date Topic Reading Homework assigned Homework due Solutions Project
17-Jan Introduction Ch 1 HW0 HW0
19-Jan Performance + Benchmarks and Amdhal Law Ch 2.1 - 2.15 HW1 SOLN-HW1
24-Jan MIPS ISA Skim Ch 2.17 and 2.18
26-Jan Verilog Tutorial (slides above) See slides and cheat sheet
31-Jan Arithmetic & Logic See slides and cheat sheet
2-Feb Processor (datapath) Ch 3 and Appendix B.1-B.6 HW2 HW1 SOLN-HW2 Form project team (Feb 8th)
7-Feb Processor (control path) Ch 3 and Appendix B.1-B.6
9-Feb Processor (pipelining) Ch 4.1 - 4.10
14-Feb Processor (pipelining) Ch 4.1 - 4.10 HW3 HW2 SOLN-HW3 Project plan
16-Feb Processor (pipeline hazards) Ch 4.1 - 4.10
21-Feb Processor (pipeline hazards) Ch 4.1 - 4.10
23-Feb Processor (Superscalar) Skim 4.11 and 4.12 Design Review
28-Feb Processor (MIPS R10000) Ch 1.6 - 1.10 HW4 HW3 SOLN-HW4
2-Mar Mid term review
7-Mar Mid term 1
9-Mar Cache concepts
14-Mar Cache design Ch 5.1-5.2 Demo 1
16-Mar Cache design Ch 5.3
21-Mar Spring break
23-Mar Spring break
28-Mar Cache Performance Ch 5.9
30-Mar Virtual memory CH 5.4-5.8 HW5 HW4 SOLN-HW5
4-Apr Virtual memory CH 5.4-5.8
6-Apr Virtual memory review ch 5.8
11-Apr No class Ch 5.11 Demo 2
13-Apr Main memory and ECC See ECC handout HW6 HW5 SOLN-HW6 Cache FSM turnin
18-Apr IO Ch 6.1-6.3
20-Apr Parallel processors/shared memory Ch 6.4-6.5 Cache Demo
25-Apr Advanced Arithmetic Ch 6.6
27-Apr GPU (1) no reading
2-May GPU (2) no reading
4-May Final review HW6
7-May Final exam
9-May Final demo Final demo
10-May Final Report Final report

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