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Disk Storage

  • Disk access time can be broken up as follows:
    • Seek time
    • Rotational delay -- measured in RPM.
    • Transfer time(rate)
  • Reliability of disks
    • Failure Rates
      • How long/life time to fail? MTTF (Mean Time to Failure)
      • How long to recover? MTTR (Mean Time to Recover)
      • The availability of a disk can thus be given as :- Availability = MTTF/(MTTF + MTTR)
  • The problem of growing need for storage and bandwidth can be solved by single large disks. However, single large disks are limited in terms of reliability and performance. An array of disks can survive disk failures, consumes less power and increases bandwidth because of parallel read/writes. The availability/capacity/bandwidth can be altered by designing storage systems based on RAID configurations. The term RAID which stands for Redundant Array of Independent Disks is introduced, described and analyzed. There are various ways in which this redundancy can be used, termed as RAID levels.
  • The various levels are RAID0 which is striping, RAID1 is mirroring, RAID2 is bitwise ECC, RAID4 is block parity and RAID5 is distributed parity. RAID2 and RAID3 are similar but RAID2 needs more disks. RAID5 is an improvement over RAID4 as it distributes the parity further increasing the parallelism. The bus is faster than the disk, this is what a disk array leverages for getting the improved performance.
  • For recovering from more than failure - we use RAID6 or use groups of RAID. Examples of such configurations(groups of disks) are RAID10 and RAID01.
  • Recovery/Repair

Mean time to recovery (MTTR): In RAID that include redundancy for reliability, this is the time following a failure to restore an array to its normal failure-tolerant mode of operation. This includes time to replace a failed disk mechanism as well as time to re-build the failed disk. (i.e. to replicate data for redundancy).

  • I/O
    • I/O buses/communication.
      • Bus allows multiple readers/writers to communicate with a device or one another. Buses used a single shared communication channel.
      • Bus Hierarchy
        • S/W System
        • Protocol
        • Timing and Signalling
        • Wires
        • Electrical Specification
      • The method of controlling the bus is done by an arbiter(bus master)
      • Daisy Chain Arbiter : The requesting device or devices assert the signal bus_request. The bus arbiter returns the bus_grant signal, which passes through each of the devices which can have access to the bus. Here, the priority of a device depends on its position in the daisy chain. If two or more devices request the bus at the same time, the highest priority device is granted the bus first, then the bus_grant signal is passed further down the chain. Generally a third signal (bus_release) is used to indicate to the bus arbiter that the first device has finished its use of the bus. Holding bus_request asserted indicates that another device wants to use the bus. This is an example of centralized Arbiter.
      • Distributed Arbiter
        • Self Selection Arbiter

Here, the devices themselves determine which of them has the highest priority. Each device has a bus_request line or lines on which it places a code identifying itself. Each device examines the codes for all the requesting devices, and determines whether or not it is the highest priority requesting device.

  • Collision Arbiter: This employs backoff method in case of bus conflicts. The employed backoff methods can be exponential.
  • Software Interface for I/O
  • ISA Level
  • System Software
  • Processor - Device interaction: The job of a processor entails how to initiate communication with the device, receive communications from the device.
    • Initiate Communication: Memory mapped I/O:- Set of addresses in memory used to communicate with the device.
    • Receive Communication: Interrupts and Polling.
    • DMA: Transfer without continuous processor involvement. The processor hands off the source, dest address and number of bytes to the DMA controller. The DMA controller performs the operations and interrupts the processor on completion. The DMA is also memory mapped.
  • System Software Support
    • Required for protection and security issues.
    • Make an easy interface for use.

Page last modified on April 29, 2008, visited 699 times

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