CS552 Course Wiki: Spring 2017 | Main »
## Homework 2 |

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Tasks |
- 1. Problem 1
- 2. Problem 2
- 3. Problem 3
- 4. Problem 4
- 5. Problem 5
- 6. Problem 6
- 7. Problem 7
- 8. Problem 8
- 9. Problem 9
- 10. Problem 10
- 11. Problem 11
- 12. Problem 12
- 13. Problem 13
- 14. Problem 14
- 15. Problem 15
Problem 1 and 2 can be done alone or with a partner. Names must be included in the partners.txt file included in the supplied tar file. Submitted: - Problems 1 & 2
- Electronic submission of files: Submit to learn@UW, One submission per pair, titled hw2.tar
Not Submitted: - Problems 3 - 14:
- These problems are optional and will not be graded but are recommended for a better understanding of the course material.
- This homework uses Verilog for the first two problems.
- Read the Simulating Verilog Tutorial in the Tools page.
- Read the Verilog rules in the Tools page.
- Read Verilog rules check in the Tools page. Your program must pass Vcheck.
- Review The elements of Logic Design Style
- Homework is due at start of class
- An example of using the question 1 testbench and expected output can be seen on the Homework 2 Demo page.
- A tarball is provided that includes testbenches and top level module definitions for all verilog problems: hw2.tar
- Do not edit the provided *_hier.v files
- You must maintain the directory structure that exists in the provided tar file, i.e. each problem has its own subdirectory titled hw2_[1,2]
**All**verilog files required to run your verilog must be in each problem's respective subdirectory. You may need to have copies of some files in each directory.- Vcheck output for all modules you have written.
- A legible schematic.pdf file must be in each problem's respective subdirectory with the schematics you drew.
**Any solution without a corresponding schematic drawing will NOT be graded**- A scanner is available for general use in Wendt Library
- The partners.txt file at the top level of the tarball must contain the names of yourself and your partner.
- Submit only this tar file named hw2.tar - only one partner needs to submit the file
## 1. Problem 1Design a 16-bit barrel shifter with the following interface. Consult lecture notes for barrel shifter design. Inputs: - [15:0]In - 16 bit input operand value to be shifted
- [3:0]Cnt - 4 bit amount to shift (number of bit positions to shift)
- [1:0]Op - shift type, see encoding in table below
Output: - [15:0]Out - 16 bit output operand
Before starting to write any verilog, you should do the following: - Break down your design into sub-modules.
- Define interfaces between these modules
- Draw paper and pencil schematics for these modules (these will he handed in as scanned schematic.pdf file)
- Then start writing verilog
Verify the design using the testbench in the supplied tar file. For a simple walk-through of how to run the testbench and example outputs see the Homework 2 Demo page. ## 2. Problem 2This problem should also be done in Verilog. Design a simple 16-bit ALU. Operations to be performed are 2's Complement ADD, bitwise-OR, bitwise-XOR, bitwise-AND, and the shift unit from problem 1. In addition, it must have the ability to invert either of its data inputs before performing the operation and have a Cin input (to enable subtraction). Another input line also determines whether the arithmetic to be performed is signed or unsigned . Use a carry look-ahead adder (CLA) in your design. (Hint: First design a 4-bit CLA. Then use blocks of this CLA for designing the 16-bit CLA.) For all the shift and rotate operations, assume the number to shift is input A to ALU and the shift/rotate amount is bits [3:0] of input B.
The external interface of the ALU should be:
- A[15:0], B[15:0] - Data input lines A and B (16 bits each.)
- Cin - A carry-in for the LSB of the adder.
- Op(2:0) - The OP code (3 bits.) The OP code determines the operation to be performed. The opcodes are shown in the Table above.
- invA - An invert-A input (active high) that causes the A input to be inverted before the operation is performed.
- invB - An invert-B input (active high) that causes the B input to be inverted before the operation is performed.
- sign - A signed-or-unsigned input (active high for signed) that indicates whether signed or unsigned arithmetic to be performed for ADD function on the data lines. (This affects the Ofl output.)
- Out(15:0) - Data out (16 bits.)
- Ofl - (1 bit) This indicates high if an overflow occurred.
- Zero - (1 bit) This indicates that the result is exactly zero.
Other assumptions: - You can assume 2's complement numbers.
- In case of logic functions, Ofl is not asserted (i.e. kept logic low).
Top level module definitions and a testbench is included in the supplied tar file. Simulate and verify your design using the supplied testbench or create one yourself to test any of your submodules. You must reuse the shift unit designed in Problem 1. Again, before starting to write any verilog, you should do the following: - Break down your design into sub-modules.
- Define interfaces between these modules
- Draw paper and pencil schematics for these modules (these will he handed in as schematic.pdf file)
- Then start writing verilog
The remaining problems will not be graded but are recommended for better understanding of the course material. ## 3. Problem 3Do problem 1.3 from textbook ## 4. Problem 4Do problem 1.4 from textbook ## 5. Problem 5Do problem 2.1 from textbook ## 6. Problem 6Do problem 2.2 from textbook ## 7. Problem 7Do problem 2.3 from textbook ## 8. Problem 8Do problem 2.14 from textbook ## 9. Problem 9Do problem 2.15 from textbook ## 10. Problem 10Do problem 2.16 from textbook ## 11. Problem 11Do problem 2.17 from textbook ## 12. Problem 12Do problem 2.18.1 to 2.18.3 from textbook ## 13. Problem 13Do problem 2.19.1 to 2.19.3 from textbook ## 14. Problem 14Do problem 2.25.1 to 2.25.2 from textbook ## 15. Problem 15Do problem 2.26.1 to 2.26.3 from textbook |

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