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In this problem, you must design a FIFO that can hold 64-bit data values. Design, simulate, and verify in Verilog, a 4-entry FIFO that can hold 64-bit data. The FIFO should implement the functionality of a conventional first-in-first-out data structure. You may assume the D-flip flop module provided. The FIFO accepts new input each cycle when the data_in_valid is asserted, unless it is full (indicated by fifo_full). Data that is inserted into a full FIFO is ignored. The data_out signal is always driven by the data at the head of the FIFO (the oldest data). The head of the FIFO is popped when pop_fifo is asserted. An empty FIFO drives zeros on data_out and asserts fifo_empty. Popping an empty FIFO has no effect. Asserting reset makes the FIFO empty. All outputs should change only in response to the clock edge.
The "err" output is a standard way of indicating hardware errors or illegal states. Assert it (1'b1) for states which are supposed to be impossible to get into.
Do not make any changes to the provided
You must verify your design using the testbench in the supplied tar file. Run the testbench in your hw4_1 directory using the command
The testbench for this problem (fifo_bench.v) consists of 145 randomly generated test cases. Each test case asserts a set of input signals to your module, and after one cycle, compares outputs from your module with the outputs that are expected from a perfect FIFO implementation.
If there are no errors in your design you will see a "TEST PASSED" message. If the testbench failed with a "TEST FAILED" message, there are 3 possible reasons:
Above each of these error messages you will see the inputs to your module, your outputs and the expected outputs for that cycle which can help you debug. If you have only "MINORCHECK" errors in your submission, you will get a maximum of 85% for this problem.
Read the synthesis tutorial on the Synthesis page.
Synthesize your FIFO from problem 1. Synthesis will create the 'synth' directory which will include fifo.syn.v, area report, timing report, etc. Do not delete this directory, copy this output to the hw4_2 directory - it must be included in your submission. Make sure that in the area report no cell has an area of zero
Develop instruction level tests for your processor. In this problem each one of you will develop a set of small programs that are meant to test whether your processor implements these instructions correctly. You will write these programs in assembly, run them on an instruction emulator to make sure what you wrote is indeed testing the right thing. The eventual goal is to run these programs on your processor's verilog implementation and use them to test your implementation.
Info about how to write assembly code and also about how to use the assembler can be found in the Using the assembler page. Details about what each instruction means is available in the ISA specification page.
Each team will be responsible for one randomly assigned instruction (along with common instructions jal, jalr) and must develop a set of simple programs for that instructions. Each team will also have to write programs for jal, jalr instructions along their assigned instruction. The table below gives the assignment of instructions to each team.
Note: I got the list of teams from the design review signups. If you didn't do the design review you likely aren't on the list. Please contact me and you'll be added.
To get you started below are two example tests for the add instruction.
You will notice one thing. The
The work flow we will follow is:
Read the following two documents on how to use to assembler and simulator:
Below is a short demo:
The simulator will print a trace of each instruction along with the state of the relevant registers. You should examine these to make sure that your test is indeed doing what is expected.
What you need to do:
Indicate all of the true, anti-, and output-dependences in the following segment of MIPS assembly code:
xor $1, $2, $3 and $4, $5, $6 sub $7, $4, $5 add $5, $1, $5 sw $4, 100($7) or $4, $7, $4
For the code above, which of the dependences will manifest themselves as hazards in the pipeline in Figure 4.41 on page 355 of COD4e? How are these hazards resolved in this pipeline? Assuming the 'xor' instruction enters fetch (F) in cycle 1, in what cycle does the 'or' instruction enter writeback (W)? Show your work in a pipeline diagram. (Assume that the register file cannot read and write the same register in the same cycle and get the new data.)
How does your answer change if you consider the pipeline in 4.60, on page 375 of COD4e? (Assume that the register file contains internal bypassing and can read and write the same register in the same cycle and get the new data.)
Consider the following assembly program to be executed in a MIPS ISA 5-stage(F,D,X,M,W) pipelined data path given in figure 4.51 on page 362 of COD4e:
I1: add $3,$4,$6 I2: sub $5,$3,$2 I3: lw $6,100($5) I4: add $5,$6,$3
a) Identify every occurrence and every types of data dependencies True(RAW), Anti(WAR), Output(WAW) in the above problem. Also, indicate which register is involved in that data dependency.
b) If this program is to be executed in a pipelined data path, create a pipeline timing diagram table(clock cycle numbers as column and instructions as rows)assuming NO forwarding, except that register forwarding is available.
c) Identify all the data hazards that may occur as applicable. For each hazard, indicate whether data forwarding(including register forwarding) may be applied to eliminate that hazard. For each hazard, give the two instructions involved, the register involved, and the pipeline register(IF/ID, ID/EX, EX/MEM, MEM/WB)whose output will be used for data forwarding.
Consider the following program code:
lw $s1, 8($s0) sub $s0,$s1,$S2 add $s0,$s0,$s1
If the above program is to be executed in a pipelined datapath given in figure 4.51 on page 362 of COD4e equipped with full data forwarding (as well as register forwarding), complete the timing diagram table(clock cycle numbers as column and instructions as rows). Also mark the clock cycle when a data forwarding(F) takes place or a pipeline stall(S) is inserted.
Consider the following code sequence and the datapath in figure 4.51 on page 362 of COD4e. Assuming the first instruction is fetched in cycle 1 and the branch is not taken, in which cycle does the 'and' instruction write its value to the register file? What if the branch IS taken? (Assume no branch prediction). Show pipeline diagrams.
beq $2, $3, foo add $3, $4, $5 sub $5, $6, $7 or $7, $8, $9 foo: and $5, $6, $7
Consider the pipeline in Figure 4.51 on page 362; assume predict-not-taken for branches and assume a "Hazard detection unit" in the ID stage as shown on page 379. Can an attempt to flush and an attempt to stall occur simultaneously? If so, do they result in conflicting actions and/or cooperating actions? If there are any cooperating actions, how do they work together? If there are any conflicting actions, which should take priority? What would you do in the design to make sure this works correctly? You may want to consider the following code sequence to help you answer this question:
beq $1, $2, TARGET #assume that the branch is taken lw $3, 40($4) add $2, $3, $4 sw $2, 40($4) TARGET: or $1, $1, $2
Consider the following MIPS assemble code segment:
bne $s1,$s2,LABEL // $s1 != $s2 add $t2,$t1,$s1 sw $t2,4($s1) j EXIT LABEL: lw $s1,4($s6) EXIT: addi $s1,$s1,4
Assume this code segment on a pipelined data path with data forwarding depicted in figure 4.65 on page 384 of COD4e where the branch decision is made in ID stage.
Assuming $s1 != $s2, a control hazard will occur. Provide a timing diagram table (clock cycle numbers as column and instructions as rows), to show which instructions are running at which phase (F,D,X,M,W)at each clock cycle. If an instruction is flushed from the pipeline, then the remaining phases should not appear. If an instruction is stalled for one cycle, then the remaining phases will be pushed back by one cycle. Indicate on the clock cycle and corresponding instruction for any flush or stall action. (No branch predictors are used in this problem).
During the execution of a program, conditional branches have been executed 15 times. The traces of TAKEN(T) and NOT-TAKEN(N) of each branch instruction are listed below:
a) Prediction accuracy for "always NOT TAKEN" =
b) Prediction accuracy for "1 - bit predictor" =
Indicate output of predictor for each instruction traced. Outcome = 1 if correct, and 0 if incorrect.
c) Prediction accuracy for "2 - bit predictor" =
Indicate output of predictor for each instruction traced. Outcome = 1 if correct, and 0 if incorrect.
Note: For dynamic predictors (1 bit and 2 bit), assume the first predicted entry as TAKEN (T) and then proceed.
High performance datapaths use bypass paths (also known as data forwarding logic) to reduce pipeline stalls. However, bypass paths are relatively expensive, especially in some wire constrained technologies. To reduce the cost (and potential cycle time impact), some architects have explored omitting some of the possible bypass paths. Consider the datapath illustrated below (note that the PC update logic and all control logic is intentionally omitted). This pipelined datapath is similar to the one in the book, but only has bypass paths on one side of the ALU. Assume that the register file intentionally bypasses the value, so that if register Si is read and written in the same cycle, then the read returns the new value. Assume that the control logic bypasses the data as soon as possible using the given forwarding data paths, and stalls in decode otherwise. You may NOT add additional data paths.
In this problem, you will look at how a program snippet performs on this pipleline. Recall that R-format instructions have the form: opcode rd, rs, rt
and I-format instructions have the form: opcode rt, imm(rs) or opcode rt, rs, imm
Use the table given below to show how the given instruction sequence flows through the pipeline and where stalls are necessary to resolve hazards.
Consider the code and pipeline above. Show the execution of this code on the pipeline above. Use the letters, F, D, X, M, and W.
For each cycle where a stall occurs explain why ?
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