From CS552 Course Wiki: Spring 2017

Main: HW5Problem1AddressTraceTable

Print this table and fill in the values by hand and turn it in with your submission. Run each trace using mem_system_perfbench. Determine when the events listed in the table occur and write down the cycle number. This should be an in integer and should be the DUT/clkgen/cycle_count signal. This is NOT the raw simulation time that vsim shows you.

The first row is filled up as 3 because I am assuming your cache can accept a request in the cycle immediately after reset, which is cycle 3 in our testbench.

  1. mem1.addr
  2. mem2.addr
  3. mem3.addr
  4. mem4.addr
  5. mem5.addr
  6. mem6.addr
  7. mem7.addr
  8. mem8.addr

Description of traces Copy from here: /u/k/a/karu/courses/cs552/spring2009/handouts/verilog_code/hw5-mem/test_traces

Event Cycle count
mem1.addr
ld (0 1 348 0) (arrives in mem_system) 3
Reply back to processor (Done == 1)
mem2.addr
Second ld (0 1 348 0) (arrives in mem_system)
Reply back to processor (Done == 1)
mem3.addr
1 0 348 24 (arrives in mem_system)
Stall goes low
Done goes high
mem4.addr
1 0 348 24 (arrives in mem_system)
Stall goes low
Done goes high
mem5.addr
0 1 2396 0 (arrives in mem_system)
Reply back to processor (Done == 1)
mem6.addr
0 1 2396 0 (arrives in mem_system)
Reply back to processor (Done == 1)
mem7.addr
1 0 2396 24 (arrives in mem_system)
Stall goes low
Done goes high
mem8.addr
1 0 2396 32 (arrives in mem_system)
Stall goes low
Done goes high
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Page last modified on April 12, 2011, at 09:02 AM