From CS552 Course Wiki: Spring 2017

Main: HW5Problem2AddressTraceTable

Print this table and fill in the values by hand and turn it in with your submission. Run each trace using mem_system_perfbench. Determine when the events listed in the table occur and write down the cycle number. This should be an in integer and should be the DUT/clkgen/cycle_count signal. This is NOT the raw simulation time that vsim shows you.

The first row is filled up as 3 because I am assuming your cache can accept a request in the cycle immediately after reset, which is cycle 3 in our testbench.

  1. mem_2way1.addr
  2. mem_2way2.addr
  3. mem_2way3.addr
  4. mem_2way4.addr
  5. mem_2way5.addr
  6. mem_2way6.addr
  7. mem_2way7.addr

Copy from here: /u/k/a/karu/courses/cs552/spring2013/handouts/verilog_code/hw5-mem/test_traces

Description of traces

Event Cycle count
mem_2way1.addr
ld (0 1 348 0) (arrives in mem_system) 3
Reply back to processor (Done == 1)
mem_2way2.addr
Third ld (0 1 348 0)
Reply back to processor (Done == 1)
mem_2way3.addr
st (1 0 348 56) (arrives in mem_system)
Reply back to processor (Done == 1)
mem_2way4.addr
Third st (1 0 348 23) (arrives in mem_system)
Reply back to processor (Done == 1)
mem_2way5.addr
Third ld (0 1 4444 0) (arrives in mem_system)
Reply back to processor (Done == 1)
mem_2way6.addr
Third st (1 0 4444 61) (arrives in mem_system)
Reply back to processor (Done == 1)
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Page last modified on April 07, 2013, at 10:16 PM