From CS552 Course Wiki: Spring 2017

Main: Homework 6

Homework 6

Due 05/04
Weight: 15%

Problem 1 must be done with your project partner. Names must be included in the partners.txt file included in the supplied tar file.

Submitted:

Not Submitted:

The remaining problems will not be graded but are recommended for better understanding of the course material.

Problem 2

Consider the example single-error-correcting code with a minimum Hamming distance of three example in the ECC1 handout. The handout can be found at the bottom of this page

  1. Find the codewords for these datawords :
    1. 00000111
    2. 10001111
    3. 11001010
    4. 10101001
  2. For this part assume that at most one bit can be in error. If the following values are read from the memory (stored using the above encoding in the order C3 C2 C1 C0 b7 b6 b5 b4 b3 b2 b1 b0), find the correct dataword.
    1. 0011 11111111
    2. 0011 01111111
    3. 1110 00011111
    4. 0111 10001011

Problem 3 (review of chapter-3)

  1. Show the IEEE 754 binary representation for the floating point number 17.384 (base 10)
  2. Convert the following number given in IEEE 754 binary representation to the equivalent decimal number
    0000 0100 0000 0100 1001 0000 1001 0110

This is a good reference on IEEE 754 standard; link

Problem 4

Virtual Memory: Consider a byte addressable system with 1GB physical memory and 4GB of virtual address space and no caching.

1) What should be the width of the address bus within the processor (prior to address translation)? What should be the width of the address bus after address translation?

2) Assume that the system uses 4KB pages. How many page table entries are required per process, (assuming that all processes uses all 4GB of the virtual address space)?

3) Now we are adding a TLB to speed up address translation. The TLB is fully associative with only four entries. The snapshot of the TLB and the contents of the relevant portion of the page table are shown below. Explain why the tags are 20 bits wide and why the physical page numbers are 18 bits wide.

TLB snapshot:

Valid Tag Physical page number
1 20'h0000B 18'h0000C
1 20'h00007 18'h00004
1 20'h00003 18'h00006
0 20'h00004 18'h00009

Page table snapshot:

Valid Physical page or in disk
1 18'h00005
0 <In Disk>
0 <In Disk>
1 18'h00006
1 18'h00009
1 18'h0000B
0 <In Disk>
1 18'h00004
0 <In Disk>
0 <In Disk>
1 18'h00003
1 18'h0000C

Problem 5

Consider the same system of Problem 6 and the snapshot of TLB and page tables for a given process.

1)Given that this process generates the following stream of virtual addresses:

32'h0000_7000

32'h0000_B000

32'h0000_3000

32'h0000_BA5A

32'h0000_BFFF

32'h0000_AA5A

32'h0000_5FFF

32'h0000_1CCC

Classify each access as TLB hit/Page table hit/Page fault.

2)For each memory access which is not a page fault, what is the translated physical address?


Problem 6

What are types of programs or problems that are not suitable for GPUs? Give one example. You may describe an algorithm, psuedo-code or c-code. Justify why you think that the performance of this algorithm will be bad on GPUs.


Problem 7

Something about cache-coherence and multiprocessors here. TBD


Problem 8

Something about cache-coherence and multiprocessors here. TBD


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Page last modified on April 15, 2017, at 02:42 PM