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WISC-SP13 Instruction Set Architecture

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WISC-SP13 Instruction Set Architecture

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  1. 1. Instruction Summary
  2. 2. Formats
    1. 2.1 J-format
    2. 2.2 I-format
    3. 2.3 R-format
  3. 3. Special Instructions

1.  Instruction Summary

Instruction FormatSyntaxSemantics
00000 xxxxxxxxxxxHALTCease instruction issue, dump memory state to file
00001 xxxxxxxxxxxNOPNone
 
01000 sss ddd iiiiiADDI Rd, Rs, immediateRd <- Rs + I(sign ext.)
01001 sss ddd iiiiiSUBI Rd, Rs, immediateRd <- I(sign ext.) - Rs
01010 sss ddd iiiiiXORI Rd, Rs, immediateRd <- Rs XOR I(zero ext.)
01011 sss ddd iiiiiANDNI Rd, Rs, immediateRd <- Rs AND ~I(zero ext.)
10100 sss ddd iiiiiROLI Rd, Rs, immediateRd <- Rs <<(rotate) I(lowest 4 bits)
10101 sss ddd iiiiiSLLI Rd, Rs, immediateRd <- Rs << I(lowest 4 bits)
10110 sss ddd iiiiiRORI Rd, Rs, immediateRd <- Rs >>(rotate) I(lowest 4 bits)
10111 sss ddd iiiiiSRLI Rd, Rs, immediateRd <- Rs >> I(lowest 4 bits)
10000 sss ddd iiiiiST Rd, Rs, immediateMem[Rs + I(sign ext.)] <- Rd
10001 sss ddd iiiiiLD Rd, Rs, immediateRd <- Mem[Rs + I(sign ext.)]
10011 sss ddd iiiiiSTU Rd, Rs, immediateMem[Rs + I(sign ext.)] <- Rd
Rs <- Rs + I(sign ext.)
 
11001 sss xxx ddd xx BTR Rd, RsRd[bit i] <- Rs[bit 15-i] for i=0..15
11011 sss ttt ddd 00ADD Rd, Rs, RtRd <- Rs + Rt
11011 sss ttt ddd 01SUB Rd, Rs, RtRd <- Rt - Rs
11011 sss ttt ddd 10XOR Rd, Rs, RtRd <- Rs XOR Rt
11011 sss ttt ddd 11ANDN Rd, Rs, RtRd <- Rs AND ~Rt
11010 sss ttt ddd 00ROL Rd, Rs, RtRd <- Rs << (rotate) Rt (lowest 4 bits)
11010 sss ttt ddd 01SLL Rd, Rs, RtRd <- Rs << Rt (lowest 4 bits)
11010 sss ttt ddd 10ROR Rd, Rs, RtRd <- Rs >> (rotate) Rt (lowest 4 bits)
11010 sss ttt ddd 11SRL Rd, Rs, RtRd <- Rs >> Rt (lowest 4 bits)
11100 sss ttt ddd xxSEQ Rd, Rs, Rtif (Rs == Rt) then Rd <- 1 else Rd <- 0
11101 sss ttt ddd xxSLT Rd, Rs, Rtif (Rs < Rt) then Rd <- 1 else Rd <- 0
11110 sss ttt ddd xxSLE Rd, Rs, Rtif (Rs <= Rt) then Rd <- 1 else Rd <- 0
11111 sss ttt ddd xxSCO Rd, Rs, Rtif (Rs + Rt) generates carry out
then Rd <- 1 else Rd <- 0
 
01100 sss iiiiiiiiBEQZ Rs, immediateif (Rs == 0) then
PC <- PC + 2 + I(sign ext.)
01101 sss iiiiiiiiBNEZ Rs, immediateif (Rs != 0) then
PC <- PC + 2 + I(sign ext.)
01110 sss iiiiiiiiBLTZ Rs, immediateif (Rs < 0) then
PC <- PC + 2 + I(sign ext.)
01111 sss iiiiiiiiBGEZ Rs, immediateif (Rs >= 0) then
PC <- PC + 2 + I(sign ext.)
11000 sss iiiiiiiiLBI Rs, immediateRs <- I(sign ext.)
10010 sss iiiiiiiiSLBI Rs, immediateRs <- (Rs << 8) | I(zero ext.)
 
00100 dddddddddddJ displacementPC <- PC + 2 + D(sign ext.)
00101 sss iiiiiiiiJR Rs, immediatePC <- Rs + I(sign ext.)
00110 dddddddddddJAL displacementR7 <- PC + 2
PC <- PC + 2 + D(sign ext.)
00111 sss iiiiiiii JALR Rs, immediateR7 <- PC + 2
PC <- Rs + I(sign ext.)
 
00010siic Rsproduce IllegalOp exception. Must provide one source register.
00011 xxxxxxxxxxxNOP / RTIPC <- EPC

2.  Formats

WISC-SP13 supports instructions in four different formats: J-format, 2 I-formats, and the R-format. These are described below.

2.1  J-format

The J-format is used for jump instructions that need a large displacement.



J-Format

5 bits11 bits
Op CodeDisplacement

Jump Instructions

The Jump instruction loads the PC with the value found by adding the PC of the next instruction (PC+2, not PC+4 as in MIPS) to the sign-extended displacement.

The Jump-And-Link instruction loads the PC with the same value and also saves the address of the next sequential instruction (i.e., PC+2) in the link register R7.

The syntax of the jump instructions is:

  • J displacement
  • JAL displacement

2.2  I-format

I-format instructions use either a destination register, a source register, and a 5-bit immediate value; or a destination register and an 8-bit immediate value. The two types of I-format instructions are described below.

I-format 1 Instructions

I-format 1

5 bits3 bits3 bits5 bits
Op CodeRsRdImmediate

The I-format 1 instructions include XOR-Immediate, ANDN-Immediate, Add-Immediate, Subtract-Immediate, Rotate-Left-Immediate, Shift-Left-Logical-Immediate, Rotate-Right-Immediate, Shift-Right-Logical-Immediate, Load, Store, and Store with Update.

The ANDNI instruction loads register Rd with the value of the register Rs AND-ed with the one's complement of the zero-extended immediate value. (It may be thought of as a bit-clear instruction.) ADDI loads register Rd with the sum of the value of the register Rs plus the sign-extended immediate value. SUBI loads register Rd with the result of subtracting register Rs from the sign-extended immediate value. (That is, immed - Rs, not Rs - immed.) Similar instructions have similar semantics, i.e. the logical instructions have zero-extended values and the arithmetic instructions have sign-extended values.

For Load and Store instructions, the effective address of the operand to be read or written is calculated by adding the value in register Rs with the sign-extended immediate value. The value is loaded to or stored from register Rd. The STU instruction, Store with Update, acts like Store but also writes Rs with the effective address.

The syntax of the I-format 1 instructions is:

  • ADDI Rd, Rs, immediate
  • SUBI Rd, Rs, immediate
  • XORI Rd, Rs, immediate
  • ANDNI Rd, Rs, immediate
  • ROLI Rd, Rs, immediate
  • SLLI Rd, Rs, immediate
  • RORI Rd, Rs, immediate
  • SRLI Rd, Rs, immediate
  • ST Rd, Rs, immediate
  • LD Rd, Rs, immediate
  • STU Rd, Rs, immediate

I-format 2 Instructions

I-format 2

5 bits3 bits8 bits
Op CodeRsImmediate

The Load Byte Immediate instruction loads Rs with a sign-extended 8 bit immediate value.

The Shift-and-Load-Byte-Immediate instruction shifts Rs 8 bits to the left, and replaces the lower 8 bits with the immediate value.

The format of these instructions is:

  • LBI Rs, signed immediate
  • SLBI Rs, unsigned immediate

The Jump-Register instruction loads the PC with the value of register Rs + signed immediate. The Jump-And-Link-Register instruction does the same and also saves the return address (i.e., the address of the JALR instruction plus one) in the link register R7. The format of these instructions is

  • JR Rs, immediate
  • JALR Rs, immediate

The branch instructions test a general purpose register for some condition. The available conditions are: equal to zero, not equal to zero, less than zero, and greater than or equal to zero. If the condition holds, the signed immediate is added to the address of the next sequential instruction and loaded into the PC. The format of the branch instructions is

  • BEQZ Rs, signed immediate
  • BNEZ Rs, signed immediate
  • BLTZ Rs, signed immediate
  • BGEZ Rs, signed immediate

2.3  R-format

R-format instructions use only registers for operands.
R-format

5 bits3 bits3 bits3 bits2 bits
Op CodeRsRtRdOp Code Extension
ALU and Shift Instructions

The ALU and shift R-format instrucions are similiar to I-format 1 instructions, but do not require an immediate value. In each case, the value of Rt is used in place of the immediate. No extension of its value is required. In the case of shift instructions, all but the 4 least-significant bits of Rt are ignored.

The ADD instruction performs signed addition. The SUB instruction subtracts Rs from Rt. (Not Rs - Rt.) The set instructions SEQ, SLT, SLE instructions compare the values in Rs and Rt and set the destination register Rd to 0x1 if the comparison is true, and 0x0 if the comparison is false. SLT checks for Rs less than Rt, and SLE checks for Rs less than or equal to Rt. (Rs and Rt are two's complement numbers.) The set instruction SCO will set Rd to 0x1 if Rs plus Rt would generate a carry-out from the most significant bit; otherwise it sets Rd to 0x0. The Bit-Reverse instruction, BTR, takes a single operand Rs and copies it to Rd, but with a left-right reversal of each bit; i.e. bit 0 goes to bit 15, bit 1 goes to bit 14, etc.

The syntax of the R-format ALU and shift instructions is:

  • ADD Rd, Rs, Rt
  • SUB Rd, Rs, Rt
  • ANDN Rd, Rs, Rt
  • ROL Rd, Rs, Rt
  • SLL Rd, Rs, Rt
  • ROR Rd, Rs, Rt
  • SRL Rd, Rs, Rt
  • SEQ Rd, Rs, Rt
  • SLT Rd, Rs, Rt
  • SLE Rd, Rs, Rt
  • SCO Rd, Rs, Rt
  • BTR Rd, Rs

3.  Special Instructions

Special instructions use the R-format. The HALT instruction halts the processor. The HALT instruction and all older instructions execute normally, but the instruction after the halt will never execute. The PC is left pointing to the instruction directly after the halt.

The No-operation instruction occupies a position in the pipeline, but does nothing.

The syntax of these instructions is:

  • HALT
  • NOP

The SIIC and RTI instructions are extra credit and can be deferred for later. They will be not tested until the final demo.

The SIIC instruction is an illegal instruction and should trigger the exception handler. EPC should be set to PC + 2, and control should be transferred to the exception handler which is at PC 0x02.

The syntax of this instruction is:

  • SIIC Rs

The source regsiter name must be ignored. The syntax is specified this way with a dummy source register, to reuse some components from our existing assembler. The RTI instruction should remain equivalent to NOP until the rest of the design has been completed and thoroughly tested.

RTI returns from an exception by loading the PC from the value in the EPC register.

The syntax of this instruction is:

  • RTI

See the Optimizations page for more information.


Page last modified on January 22, 2013, visited 2143 times

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