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1.  Lecture Schedule

This course's text readings will cover Chapters 1 through 5, Appendix A, B, and Appendix C. The list of subsections omitted will be updated below (interested students can skim over them).

  • 2.16 through 2.18
  • 4.11, 4.12
  • 5.13
Date Topic Reading Homework assigned
17-Jan Introduction Ch 1 HW0
19-Jan Performance + Benchmarks and Amdhal Law Ch 2.1 - 2.15 HW1
24-Jan MIPS ISA Skim Ch 2.17 and 2.18
26-Jan Verilog Tutorial (slides above) See slides and cheat sheet
31-Jan Arithmetic & Logic See slides and cheat sheet
2-Feb Processor (datapath) Ch 3 and Appendix B.1-B.6 HW2
7-Feb Processor (control path) Ch 3 and Appendix B.1-B.6
9-Feb Processor (pipelining) Ch 4.1 - 4.10
14-Feb Processor (pipelining) Ch 4.1 - 4.10 HW3
16-Feb Processor (pipeline hazards) Ch 4.1 - 4.10
21-Feb Processor (pipeline hazards) Ch 4.1 - 4.10
23-Feb Processor (Superscalar) Skim 4.11 and 4.12
28-Feb Processor (MIPS R10000) Ch 1.6 - 1.10 HW4
2-Mar Mid term review
7-Mar Mid term 1
9-Mar Cache concepts
14-Mar Cache design Ch 5.1-5.2
16-Mar Cache design Ch 5.3
21-Mar Spring break
23-Mar Spring break
28-Mar Cache Performance Ch 5.9
30-Mar Virtual memory CH 5.4-5.8 HW5
4-Apr Virtual memory CH 5.4-5.8
6-Apr Virtual memory review ch 5.8
11-Apr No class Ch 5.11
13-Apr Main memory and ECC See ECC handout HW6
18-Apr IO Ch 6.1-6.3
20-Apr Parallel processors/shared memory Ch 6.4-6.5
25-Apr Advanced Arithmetic Ch 6.6
27-Apr GPU (1) no reading
2-May GPU (2) no reading
4-May Final review
7-May Final exam
10-May Final Report

2.  Lecture powerpoint slides

Lecture notes can be downloaded from a UW-madison computer ( domain). If you trying to access from a machine off campus, use the common course login and password.

Lecture notes

Course organization and logistics


Arithmetic 1, Arithmetic 2


3.  Verilog Tutorial Slides, 01/28

4.  Example of well written verilog code

dyser_stage.v - this is code from a design from my research group. Notice a few things in that well written example code.

  • Parameters have been separated out into a separate file called dyser_config.v
  • Clean separation of the sequential elements and logic
  • Well written case statements
  • And some syntactic things: each input, output, wire, and reg is declared on a separate line
  • The module itself is simple and small. Hence easy to design, implement and verify. To build complex design, hierarchy is the key.

5.  Verilog cheat sheet - 02/10

Verilog cheat sheet pdf, Verilog cheat sheet word doc version if you want to edit,

6.  Other handouts and reference

Page last modified on February 10, 2016, visited 366 times

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