From CS552 Course Wiki: Spring 2017

Main: Memory-3

Here each memory block is mapped to a unique set in the cache, but within the set the memory block can be in any of the n blocks. The mapping to a set is given by: cache set = 'mem blocks' mod 'no of sets in cache'

              Cache
         0+==============+ <- set 0
          |		 |
         1+--------------+
          |		 |
         2+==============+ <- set 1
          |		 |
         3+--------------+
          |		 |
         4+==============+ <- set 2
          |		 |
         5+--------------+
          |		 |
         6+==============+ <- set 3
          |		 |
         7+--------------+
          |		 |
          +==============+
  • Since many memory blocks can be mapped to the same cache block, we need to identify which memory block is currently in a cache block. For this purpose the Most Significant (MS) bits of the memory location (block) is used. These bits constitute the tag field. Now if we divide the memory address in terms of offset, index and tag fields, we get: tag index offset. We also have a valid bit to ensure the validity of the cache line.
  • For fully associative, any line can be placed anywhere in the cache. Hence, the index bit is not present. To find a particular line in the cache, the tag is compared and the validity is checked. If tag matches and validity is set, there is a cache hit.
  • For n-way set-associative cache, there are n-entries for each cache index. The index component in the cache line is used to select a particular set. The different tags in a set can be compared in parallel. If there is a patch in tag and validity, we have a cache hit.
  • Evidently, associative caches require more hardware and are slower compared to direct mapped cache but improve conflict cache hit ratio especially for spatial workloads that may map to same cache line in a direct mapped cache. Since, associative caches can map multiple addresses in a set, introduction on new lines in the same way requires a "replacement policy" from the existing addresses. Common, replacement policies are LRU, LFU etc.
  • LRU can be simply implemented by recording timestamps with each cache block.
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Page last modified on April 10, 2008, at 12:08 PM