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Submission checklist

Tasks

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Make sure you have done the following:

  1. Each Problems X has its own folder.
  2. Everything required to run problem X should be in X's folder.
  3. Every verilog file must contain exactly 1 module, which must have the same name as the file. Run name-convention-check script on the directory.
  4. There must also not be any illegal verilog commands.
  5. For HW2-HW6 and for the project demos, turn in all verilog files including the testbench files.
    1. Note: include the provided *_hier.v file (Without any modifications)
    2. Note: include a *_hier_bench.v file which instantiates *_hier.v
  6. Run vcheck on all you design files (exclude testbench files *_hier.v and *_hier_bench.v) and turn in .vcheck.out files.

Page last modified on February 05, 2016, visited 1312 times

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