CS/ECE 752 Advanced Computer Architecture I

Spring 2007
Instructor: Karu Sankaralingam; URL: http://www.cs.wisc.edu/~karu
Meeting time: MECH ENGR 1143, 01:00 PM - 02:15 PM, MWF
Office hours: Monday,Wednesday 3-4pm, Thursday: 11-12am
TA: Derek Hower
Course URL: http://www.cs.wisc.edu/~karu/courses/cs752/Spring2007/
Mailing list: compsci752-1-s07@lists.wisc.edu


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Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course qualitatively and quantitatively examines computer design tradeoffs. We will learn, for example, how uniprocessors execute many instructions concurrently and why state-of-the-art memory systems are nearly as complex as processors. We will also learn how VLSI technology has evolved and influenced the design of ISAs and the internal working of processors. At the end of this course you will be able to appreciate the technical rationale behind the clock-speed race in the 90s, reason for its demise, and the reasons why industry is moving towards multi-core chips.


Examining tradeoffs requires that you already know how to design a correct computer. CS/ECE 552 as is taught is the important prerequisite. CS 537 is also a prerequisite, but it is less important, and may be taken concurrently or adequately covered with external reading.


Learn@UW links for this course.

I am using some parts of the Learn@UW system. You can view your grades and use the discussion board. Go to Learn@UW.



Student course evaluations are here
Today: Project presentations at 12:30PM. 4310 CS Building.
  • Meet me to discuss experimental plan and design next week (05/07-05/11)
  • Project presentations May 14th and 16th, schedule created
  • Project reports due May 18th, 2:30pm
EXAM in class at 12:30
  • Progress reports due in class 04/23.
    Look here for contents expected in progress report.
  • Exam 2 - reading list
  • Review problems added. See homework page.
  • Lecture 27 will be updated on Tuesday.
  • 03/28
    HW due on (03/30) Friday @ 1pm.
    Next week Spring break
    Paper review due in class on Monday after Spring break (04/09): David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988. Reprinted in HJ&S pp. 474-481.
    No Paper review due
    HW due on (03/30) Friday
    • Class proposal presentations on Friday (03/23).
    • Printed reports due in class, email me PDF version by 1pm.
    • Email me PPT of presentation by 12:30pm or bring your file on a USB disk to class.
    • Presentations will be graded by class - see my email from before.
    • Readings for Monday (03/26):
      1. Paper review: Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. HJ&S pp 40-49.
      2. Skim chapter 6
    No Paper reviews due in class on Wednesday (03/21).
    Skim Appendix F in text
    Paper review due in class on Monday (03/19).
    Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998.
    1. No paper reviews due for class on 03/14.
    2. Readings:
      • Read Appendix C.4 to C.6 prior to class.
      • Skim this presentation. Peter Vogt, Fully Buffered DIMM Server Memory Architecture, Talk at Intel Developers Forum, Feb. 2004
      • Skim the Cuppu et al. paper handed out last week. A performance comparison of contemporary DRAM architectures, ISCA 99.
      • Skim: Crisp R., Direct Rambus Technology: The New Main Memory Standard.
    1. Guest lecture by Prof. Michael Gleicher on Friday (03/09)
    2. No readings due
    1. Paper review due on Wednesday (03/07).
    2. Kim et al., An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches, PDF download
    1. Exam on Monday (03/05).
    2. Simics download for class.
    1. Read Balanced cache paper ( IEEE Xplore link) for class. No review due, be prepared with opinions and comments.
    2. Exam review on Friday (03/02). Prepare questions.
    3. HW3 due in class on Friday (03/02).
    1. Paper reviews due on Wednesday 02/28. See Reader 2.
      Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, ISCA 1990 , Reprinted in HJ&S pp. 395-404.
    Class meets as usual on Friday (02/23) at 1pm. GEMS Simulator tutorial.
    1. Paper reviews due on Monday 02/26
      • Joseph A. Fisher. Very Long Instruction Word architectures and the ELI-512
      • C. McNairy and D. Soltis, Itanium 2 Processor Microarchitecture
    No paper review due in class on Wednesday 02/21.
    1. Paper reviews due on Monday 02/19
      • Yeager. The MIPS R10000 Superscalar Microprocessor.
      • Sethumadhavan et al., Scalable Hardware Memory Disambiguation for High-ILP Processors.
    2. Reading: H&P skim chapter 3 and read branch prediction handout given in class.
    3. HW2 due in class.
    1. Paper review due on Wednesday 02/14
      T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, ISCA 1991. Reprinted in HJ&S pp. 228-237.
    2. Reading: H&P 2.10.
    3. The reviews page has been updated with all submitted student reviews for each paper. Next to each paper you will see a link that says, (txt, pdf).
    1. Paper review due on Monday 02/12
      Hartstein and Puzak, Optimum Power/Performance Pipeline Depth
    2. Reading: H&P 2.6-2.9, J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988. Reprinted in HJ&S pp. 202-213
    3. Make sure your CS login works
    4. No class on Friday 02/09
    1. Paper due for review on Wednesday 02/07.
      Guri Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers,
    1. Paper due for review on Monday 02/05.
      Dan Ernst, et al., A Low-Power Pipeline Based on Circuit-Level Timing Speculation
    2. Email me a question by Wendesday on: B. Sprunt. Pentium 4 performance-monitoring features. IEEE Xplore link.
    3. HW2 assigned, due 02/19
    1. Paper due for review on Friday 01/31
      Emer and D. W. Clark. A Characterization of Processor Performance in the VAX-11/780
    2. Readings: H&P Appendix A.
    3. HW#1 due in class
    1. Two papers are due for review on Wednesday 01/31
      Colwell et al., Instructions Sets and Beyond: Computers, Complexity, and Concurrency.
      Burger et al., Scaling to end of Silicon with EDGE architectures.
    2. Readings: I strongly encourage you to read appendix B and lecture notes for 01/26 describing the ISA. I will not be describing the MIPS ISA in detail in class. I will only do a short summary of the MIPS ISA.
    3. HW1 Substitute problem on memory alignment posted on homework page
    1. Projects page updated, project ideas added.
    2. Tools page updated, more to follow.
    1. Readings due in class for 01/26:
      • H&P Appendix, B.8-B-12
      • ITRS Roadmap, read/skim intro and challenges
      • Review due: Patterson, "Latency lags bandwidth"
    2. Lecture notes for Friday's lecture uploaded, both 1-on-a-page and 2-on-a-page version of slides available.
    3. Photos by email if you have not already sent me.
    4. Bring completed student info sheet to class if you did not give it to me on 01/24.
    5. Class mailing list archive enabled. Mailing list archive.
    6. Homework 1 handed out, Homeworks page on website has pdf.
    7. TA, Derek Hower has moved to new office: 6382 Computer Sciences.
    1. Reader papers with a download link that says "IEEE Xplore link" can be downloaded if you access the website from wisc.edu computer. Else you will have to go to www.lib.wisc.edu, use your NetID, and the library's E-Resources/Article Database search facility. Meet the TA during office hours if you have problems getting this to work.