CS/ECE 752 Advanced Computer Architecture I

Spring 2007
Instructor: Karu Sankaralingam; URL: http://www.cs.wisc.edu/~karu
Meeting time: MECH ENGR 1143, 01:00 PM - 02:15 PM, MWF
Office hours: Monday,Wednesday 3-4pm, Thursday: 11-12am
TA: Derek Hower
Course URL: http://www.cs.wisc.edu/~karu/courses/cs752/Spring2007/
Mailing list: compsci752-1-s07@lists.wisc.edu


Reader 2

This reader may still change slightly, and, if so, I will send email notice of changes. Links need to be verified.

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Fourth Edition, 2006.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.


  • H&P Appendix G: Vector Processors. URL http://books.elsevier.com/companions/1558605967/appendices/1558605967-appe ndix-g.pdf.
  • Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. Reprinted in HJ&S pp. 40-49.
  • Pham et al., Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor, IEEE Journal of Solid-State Circuits, January 2006 IEEE Xplore link
  • Ronny Krashinsky et al., The Vector-Thread Architecture, ISCA-31, PDF download


  • H&P Chapter 5.1-5.7
  • Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, ISCA 1990 , Reprinted in HJ&S pp. 395-404.
  • David H. Albonesi, Selective Cache Ways: On-demand Cache Resource Allocation, MICRO 1999. IEEE Xplore link
  • Changkyu Kim, Doug Burger, and Stephen W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches, ASPLOS 2002 PDF download


  • H&P Chapter 5.8 - 5.18 (skip Pentium example in 5.11 and skim 5.14, 5.15, & 5.18)
  • The PC Guide: DRAM Technologies, http://www.pcguide.com/ref/ram/tech.htm URL http://www.pcguide.com/ref/ram/tech.htm and ten Next pages (reference).
  • Peter Vogt, Fully Buffered DIMM Server Memory Architecture, Talk at Intel Developers Forum, Feb. 2004. Online PDF for University of Wisconsin only.
  • Richard Crisp, Direct Rambus Technology: The New Main Memory Standard, IEEE Micro, November-December 1997, pp. 18-28. IEEE Xplore link.
  • Vinod Cuppu, Bruce Jacbo, Brian Davis, and Trevor Mudge, A performance comparison of contemporary DRAM architectures, ISCA 99, IEEE Xplore link.
  • Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. IEEE Xplore link
  • Wen-Hann Wang, Jean-Loup Baer, and Henry M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, ISCA 1989 Reprinted in HJ&S pp. 434-442.


  • H&P Chapter 7.7-7.8, 7.10
  • David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988 June 1988. Reprinted in HJ&S pp. 474-481.
  • Peter Corbett, Bob English, Atul Goel, Tomislav Grcanac, Steven Kleiman, James Leong, and Sunitha Sankar, Row-Diagonal Parity for Double Disk Failure Correction, FAST 2004. Download link.

Multithreading and Multiprocessors

  • H&P Chapter 6.9
  • Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, ISCA 1996 Reprinted in HJ&S pp. 350-361.
  • H&P Chapter 6 Sections 6.1, 6.3, & 6.8.
  • Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29. IEEE Xplore link

Tiled Architectures

  • Sankaralingam et al., Distributed Microarchitectural Protocols in the TRIPS Prototype Processor MICRO 2006, PDF download
  • Swanson et al., Area-Performance Trade-offs in Tiled Dataflow Architectures, ISCA 2006, PDF download
  • Taylor et al., Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams, ISCA 2004 PDF download

Technology Trends

  • Shekhar Borkar, Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation, IEEE Micro 2005, November/December 2005 (Vol. 25, No. 6) pp. 10-16. IEEE Xplore link
  • John H. Edmondson, Impact of Technology on Architecture, From Design of High Performance Microprocessor Circuits, eds. Anantha Chandrakasan et al. Online PDF for University of Wisconsin only.


  • Herb-Sutter, Free Lunch is over, Dr Dobb's Journal. HTML link
  • Transactions
  • Tim Sweeney, The Next Mainstream Programming Languages, POPL 2006 Keynote, PowerPoint link


  • John Montrym and Henry Moreton, The GeForce 6800, IEEE Xplore link
  • John Owens, Streaming Architectures and Technology Trends (Chapter 29) GPU Gems 2, Nvidia Web Page, 2005. Online PDF.
  • Emmett Kilgariff and Randima Fernando. The GeForce 6 Series GPU Architecture (Chapter 30) GPU Gems 2, Nvidia Web Page, 2005 (reference). Online PDF.
  • Keith Adams and Ole Ageson. A Comparison of Software and Hardware Techniques for x86 Virtualization, Procedings of ASPLOS 2006, October 2006. Online PDF for University of Wisconsin only.
  • Jim Smith and Ravi Nair. The architecture of virtual machines, IEEE Computer, May 2005. IEEE Xplore link
  • Rich Uhlig et al. Intel virtualization technology, IEEE Computer, May 2005. IEEE Xplore link
  • Andrews J. and Baker N., Xbox 360 System Architecture IEEE Micro March-April 2006 IEEE Xplore link
  • Owens et al., A Survey of General-Purpose Computation on Graphics Hardware, Computer Graphics Forum", Volume 26, 2007. Download link