CS752 Reader2

This reader may still change slightly, and, if so, I will send email notice of changes. Links need to be verified.

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Fourth Edition, 2006.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

Static ILP

H&P Appendix G. URL: http://books.elsevier.com/companions/9781558605961/appendices/1558605967-appendix-g.pdf
• Joseph A. Fisher. Very Long Instruction Word architectures and the ELI-512 ACM download link. And a 2005 retrospective. To be reviewed
• Jerry Huck, Dale Morris, Jonathan Ross, Allan Knies, Hans Mulder, Rumi Zahir, Introducing the IA-64 Architecture, IEEE Micro Sep/Oct 2000, pp 12-23. IEEE Xplore link Reference reading
• C. McNairy and D. Soltis, Itanium 2 Processor Microarchitecture, IEEE Micro, Mar-Apr 2003, pp. 44-55. IEEE Xplore link Reference reading
• Intel (R) Itanium (R) Architecture Software Development Manual, URL: http://www.intel.com/design/itanium/manuals/iiasdmanual.htm. See especially Volume 1's (Application Architecture) Chapter 4 (Application Programming Model), 36 pages (reference). Reference reading
• R. Rau and J.A. Fisher, "Instruction-level parallel processing: History, overview, and perspective," The Journal of Supercomputing, 7(1):9-50, 1993. Reprinted in HJ&S pp. 288-308. Reference reading

Vectors

• H&P Appendix F: Vector Processors. URL http://books.elsevier.com/companions/9781558605961/appendices/1558605967-appendix-f.pdf
• Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. Reprinted in HJ&S pp. 40-49. To be reviewed
• Pham et al., Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor, IEEE Journal of Solid-State Circuits, January 2006 IEEE Xplore link To be reviewed
• Gschwind et al., Synergistic Processing in Cell's Multicore Architecture. IEEE Micro, Vol. 26, No. 2, March 2006. PDF Download. Reference reading.

Memory

• H&P Chapter 5.
• The PC Guide: DRAM Technologies, http://www.pcguide.com/ref/ram/tech.htm URL http://www.pcguide.com/ref/ram/tech.htm and ten Next pages (reference). Reference reading
• Richard Crisp, Direct Rambus Technology: The New Main Memory Standard, IEEE Micro, November-December 1997, pp. 18-28. IEEE Xplore link. Reference reading
• Vinod Cuppu, Bruce Jacbo, Brian Davis, and Trevor Mudge, A performance comparison of contemporary DRAM architectures, ISCA 99, IEEE Xplore link. To be reviewed
• Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. IEEE Xplore link To be reviewed
• Bruce Jacob and Trevor Mudge. Virtual memory: issues of implementation, Computer, vol 31, no 6, 1998. IEEE Xplore link Reference reading
• Keith Adams and Ole Ageson. A Comparison of Software and Hardware Techniques for x86 Virtualization, Procedings of ASPLOS 2006, October 2006. Online PDF for University of Wisconsin only. To be reviewed
• Jim Smith and Ravi Nair. The architecture of virtual machines, IEEE Computer, May 2005. IEEE Xplore link Reference reading
• Rich Uhlig et al. Intel virtualization technology, IEEE Computer, May 2005. IEEE Xplore link Reference reading
• Rixner et al. Memory Access Scheduling, ISCA 2000, PDF download Reference reading
• Hur and Lin, Adaptive History-Based Memory Schedulers for Modern Microprocessors, PDF download Reference reading

Storage

• H&P Chapter 6.1-6.4.
• David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988 June 1988. Reprinted in HJ&S pp. 474-481. To be reviewed
• Peter Corbett, Bob English, Atul Goel, Tomislav Grcanac, Steven Kleiman, James Leong, and Sunitha Sankar, Row-Diagonal Parity for Double Disk Failure Correction, FAST 2004. Download link. Reference reading

Multithreading and Multiprocessors

• H&P Chapter 4, skim 4.8-4.11
• Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, ISCA 1996 Reprinted in HJ&S pp. 350-361. To be reviewed
• Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29. IEEE Xplore link To be reviewed
• Herb-Sutter, Free Lunch is over, Dr Dobb's Journal. HTML link Reference reading
• Tim Sweeney, The Next Mainstream Programming Languages, POPL 2006 Keynote, PowerPoint link Reference reading

Technology Trends

• Shekhar Borkar, Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation, IEEE Micro 2005, November/December 2005 (Vol. 25, No. 6) pp. 10-16. IEEE Xplore link.Reference reading
• John H. Edmondson, Impact of Technology on Architecture, From Design of High Performance Microprocessor Circuits, eds. Anantha Chandrakasan et al. Online PDF for University of Wisconsin only. Reference reading

GPU (all reference reading)

• John Montrym and Henry Moreton, The GeForce 6800, IEEE Xplore link
• John Owens, Streaming Architectures and Technology Trends (Chapter 29) GPU Gems 2, Nvidia Web Page, 2005. Online PDF.
• Emmett Kilgariff and Randima Fernando. The GeForce 6 Series GPU Architecture (Chapter 30) GPU Gems 2, Nvidia Web Page, 2005 (reference). Online PDF.
• Andrews J. and Baker N., Xbox 360 System Architecture IEEE Micro March-April 2006 IEEE Xplore link
• Owens et al., A Survey of General-Purpose Computation on Graphics Hardware, Computer Graphics Forum", Volume 26, 2007. Download link