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CS755: VLSI Design - Fall 2008


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CS755: VLSI Design - Fall 2008

Instructor: Karu Sankaralingam; URL:
Email: Include 755 in subject line
Meeting time: TR 11:00-12:15, CS Building 1289
Office hours: M noon-1, W 11-12, Th 12:15-2, Walkin any time door open
TA: Jungseob Lee,, Office Hours: T 2:30-4:30, Th 3-4, F 2:30-3:30 (CS 5364)
Course URL:
Mailing list:

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While many of today's chips can be designed using high level hardware programming languages, an understanding of the underlying circuits is necessary to build high performance and low power systems. This course focuses on VLSI circuit design for modern CMOS technologies. The topics covered in this course include:

  • logic design,
  • high level design (Verilog),
  • basic transistor operation,
  • circuit families (static CMOS, dynamic circuits, domino),
  • clocking,
  • circuit simulation,
  • physical design, and computer-aided design tools.

The course will include regular assignments and an end-of-term design project. For the project you will design a full 16-bit processor at the transistor level and analyze area, timing, and power.

In this course, we will understand the underlying technology principles and primitives that drive architectural decisions. This is not a course on analysis of architecture and micro-architecture trade-offs. We will understand low-level circuit behavior, build high level models for analysis and use CAD tools to build processor components. At the end of this course you will be able to appreciate processor design at different levels. To summarize, take a look at this paper: Pham et al., Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor, IEEE Journal of Solid-State Circuits, January 2006. At the end of this course, you will understand all of those pieces. (paper available from machines).

Detailed topics covered:

  1. CMOS Fabrication and its implications
  2. Elementary CMOS logic design and layout
  3. MOS Device Equations
  4. CMOS Logic: Quantiative Analysis
  5. Logical Effort
  6. Interconnect
  7. Simulating Circuits
  8. Adders, Mathematical treatment of parallel prefix computation
  9. Advanced static gate design
  10. Alternatives to static logic
  11. Sequential Design
  12. Datapath
  13. SRAMs
  14. CAMs, ROMs, and PLAs
  15. MOS Devices in DSM (deep sub-micron)
  16. Circuit Pitfalls
  17. Testing
  18. Low Power desigb
  19. Design for Skew, variability
  20. Packaging, Power Supplies, and I/O
  21. Scaling and Economics
  22. Case Studies of real processors.


CS/ECE 552 or equivalent. Email instructor. Self check requirements

Page last modified on October 02, 2008

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