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Karu Sankaralingam
aka Karthikeyan Sankaralingam
Associate Professor
Computer Sciences and
Electrical and Computer Engineering

karu@cs.wisc.edu, Phone: (608) 890-0121
On Sabbatical Fall'14 and Spring '15

Research (CV)

  • I lead the Vertical Research Group.
  • Interests: Computer Architecture, Microarchitecture, VLSI, computing devices.
  • If you are a graduate or undergraduate student interested in pursuing research with me, read this.

Recent Publications

  • gem5, GPGPUSim, McPAT, GPUWattch, "Your favorite simulator here" Considered Harmful, WDDD 2014, pdf, Blog
  • Understanding the Impact of Gate-Level Physical Reliability Effects on Whole Program Execution, HPCA 2014, pdf
  • Hands-on Introduction to Computer Science at the Freshman Level, SIGCSE 2014, pdf
  • Synthesis lecture on Optimization and Mathematical Modeling in Computer Architecture,Online, Interactive demos
  • Virtually-Aged Sampling DMR: Unifying Circuit Failure Prediction and Circuit Failure Detection, MICRO 2013, pdf
  • A General Constraint-centric Scheduling Framework for Spatial Architectures, PLDI 2013, Distinguished Paper Award, pdf
  • Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures, HPCA 2013. pdf, extended tech-report, web-page
  • ConAir: Featherweight Concurrency Bug Recovery Via Single-Threaded Idempotent Execution, ASPLOS 2013, pdf
  • DySER: Unifying Functionality and Parallelism Specialization for Energy Efficient Computing, IEEE Micro Sep '12, IEEE link
  • iGPU: Exception Support and Speculative Execution on GPUs, ISCA 2012, pdf
  • Static Analysis and Compiler Design for Idempotent Processing, PLDI 2012, pdf
  • Idempotent Processor Architecture, MICRO 2011, pdf
  • Design, Integration, and Implementation of the DySER Hardware Accelerator into OpenSPARC, HPCA 2012, pdf
  • Dark Silicon and the End of Multicore Scaling, ISCA 2011, pdf; IEEE Micro Top Picks 2012,Invited ACM TOCS, Communications of ACM Research Highlights 2013
  • Sampling + DMR: Practical and Low-overhead Permanent Fault Detection, ISCA 2011, pdf
  • Dynamically Specialized Datapaths for Energy Efficient Computing, HPCA 2011, pdf
  • Relax: An Architectural Framework for Software Recovery of Hardware Faults, ISCA 2010, pdf

Research Summary

I am interested in microarchitecture, architecture, and software issues for future computation systems and lead the Vertical research group. Technology constraints of unreliable hardware, process variations, and energy efficiency are going to define computation substrates of the future. My research goal is to understand the constraints of the underlying technology and applications and use these to derive architecture and microarchitecture solutions. Vertical Research Group Page.

Students

  • Chen-han Ho
  • Sung Jin Kim
  • Tony Nowatzki
  • Newsha Ardalani
  • Vijay Thiruvengadem
  • Vinay Gangadhar

Alumni

  • Marc de Kruijf, PhD, First employment: Google
  • Emily Blem, PhD, First employment: Google
  • Venkatraman Govindaraju, PhD, First employment: Oracle
  • Raghu Balasubramanian, MS, First employment: Google
  • Jai Menon, MS
  • Shuou Nomura (previously visiting research scholar, now at Toshiba)
  • Amit Kumar, MS, First employment: Intel
  • Jesse Benson, MS, First employment: Microsoft
  • Matt Sinclair, PhD Student UIUC
  • Chris Frericks, MS, First employment: Samsung
  • Eric Harris, MS, First employment: Samsung
  • Ryan Cofell, MS
  • Zachary Marzec, MS, First employment: Qualcomm
  • Preeti Agarwal, MS, First employment: Intel
  • Michael Sartin-Tarm, BS, First employment: startup
  • Garret Staus, BS, First employment: Intel
  • Samuel Wasmundt, BS, PhD Student UCSD

Teaching (Teaching evaluations)

  • On Sabbatical Fall '14 and Spring '15

Previous courses

Education

  • B.Tech - Indian Institute of Technology, Madras, 1999
  • MS - The University of Texas at Austin, August 2006
  • PhD - The University of Texas at Austin, December 2006

Bio: Karu Sankaralingam (http://www.cs.wisc.edu/~karu) is an assistant professor in the computer sciences department at the University of Wisconsin-Madison, where he also leads the Vertical Research Group (http://www.cs.wisc.edu/vertical/). His research interests include microarchitecture, architecture, and software issues for massively parallel computation systems. He is a recipient of the IEEE TCCA Young Computer Architecture Award in 2012, an NSF CAREER award in 2009, the Emil H Steiger Distinguished Teaching award in 2014, and the Letters and Science Philip R. Certain - Gary Sandefur Distinguished Faculty Award in 2013 which recognizes outstanding teaching by a member of the College of The Letters and Science. He earned a PhD from The University of Texas at Austin in December 2006, and was the lead student architect of the TRIPS chip, a 170 million transistor chip.


Page last modified on July 31, 2014