» Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform

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Nilay Vaish, Thawan Kooburat, Lorenzo De Carli, Karthikeyan Sankaralingam, and Cristian Estan. Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform. In Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, October 2011.

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Abstract

Algorithmic solutions to the packet classification problem innetwork equipment have long been a subject of study in academia andindustry and with increases in network speeds they are becoming evenmore important. Since general purpose processors cannot meetperformance and cost requirements, researchers have been assumingthat ASICs or FPGAs are necessary for hardware implementation.Industry and academia have been working on SRAM-based platformsspecialized for tables used in network equipment, but existingpublications only describe the mapping of simpler exact match orprefix match lookups to such platforms. In this paper we adopt asoftware-hardware co-design approach mapping the EffiCuts algorithm tothe PLUG platform. Our work confirms that this solution achieves highthroughput (142 million packets per second) and low power (3.1 Watts).It identifies and evaluates changes to the original algorithm andto the platform that can improve throughput and memory utilization.

BibTeX

 @inproceedings{ancs11:plug-efficuts,
   author={Nilay Vaish and Thawan Kooburat and Lorenzo De Carli and Karthikeyan Sankaralingam and Cristian Estan},
   title={Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform},
   booktitle="{Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems}",
   year={2011},
   abstract={
 Algorithmic solutions to the packet classification problem in
 network equipment have long been a subject of study in academia and
 industry and with increases in network speeds they are becoming even
 more important. Since general purpose processors cannot meet
 performance and cost requirements, researchers have been assuming
 that ASICs or FPGAs are necessary for hardware implementation.
 Industry and academia have been working on SRAM-based platforms
 specialized for tables used in network equipment, but existing
 publications only describe the mapping of simpler exact match or
 prefix match lookups to such platforms. In this paper we adopt a
 software-hardware co-design approach mapping the EffiCuts algorithm to
 the PLUG platform. Our work confirms that this solution achieves high
 throughput (142 million packets per second) and low power (3.1 Watts).
 It identifies and evaluates changes to the original algorithm and
 to the platform that can improve throughput and memory utilization.
 },
   bib_dl_pdf = {http://bit.ly/qCz6kV},
   bib_pubtype = {Refereed Conference},
   bib_rescat = {Architecture},
   MONTH = {October}
 }

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