» Routed Inter-ALU Networks for ILP Scalability and Performance

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Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, and Doug C. Burger. Routed Inter-ALU Networks for ILP Scalability and Performance. In Proceedings of the 21st International Conference on Computer Design, pp. 170-177, October 2003.

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Abstract

Modern processors rely heavily onbroadcast networks to bypass instruction results to dependentinstructions in the pipeline. However, as clock rates increase,architectures get wider, and pipelines get deeper, broadcasting becomesmore complex, slower, and more difficult to implement. Thiscomplexity is compounded by shrinking feature size, as thecommunication speed decreases relative to transistor switching speeds.This paper examines the fundamental needs of bypassing networks andproposes a method for classifying these Inter-ALU Networks based onhow operands are routed from producers to consumers. We then proposeand evaluate at both the circuit and architectural level a fine grainpoint-to-point Routed Inter-ALU Network (RIAN) that delivers the sameor higher instruction throughput as a full bypass network but athigher speeds while using fewer wires.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @InProceedings{rian,
   author =       "Karthikeyan Sankaralingam and Vincent Ajay Singh and Stephen W. Keckler and Doug C. Burger",
   title =        "{Routed Inter-ALU Networks for ILP Scalability and Performance}",
   pages =        "170--177",
   booktitle =    "Proceedings of the 21st International Conference on Computer Design",
   year =         2003,
   month =        {October},
   abstract={Modern processors rely heavily on
 broadcast networks to bypass instruction results to dependent
 instructions in the pipeline.  However, as clock rates increase,
 architectures get wider, and pipelines get deeper, broadcasting becomes
 more complex, slower, and more difficult to implement.  This
 complexity is compounded by shrinking feature size, as the
 communication speed decreases relative to transistor switching speeds.
 This paper examines the fundamental needs of bypassing networks and
 proposes a method for classifying these Inter-ALU Networks based on
 how operands are routed from producers to consumers.  We then propose
 and evaluate at both the circuit and architectural level a fine grain
 point-to-point Routed Inter-ALU Network (RIAN) that delivers the same
 or higher instruction throughput as a full bypass network but at
 higher speeds while using fewer wires.},
   bib_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/iccd03-rian.pdf",
   bib_pubtype = {Refereed Conference},
   bib_rescat = {Architecture},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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