Information] [Resume] [Publication]
Welcome to the Home Page of SAISURESH KRISHNAKUMARAN!
I am a Graduate Student at The University of Wisconsin Madison Computer Sciences department. I did my B.E (Bachelor in Engineering) specializing in Computer Science and Engineering at College of Engineering, Guindy, Anna University, INDIA.
CS838 - Advanced Natural Language Processing
CS747 - Advanced Computer Systems Analysis Techniques
CS701 - Construction of Compilers
CS547 - Computer System Modelling Fundamentals
CS736 - Advanced Operating Systems
CS757 - Advance Computer Architecture II
Introduction to Yoga Practise
CS764 - Topics in DataBase Management
CS752 - Advance Computer Architecture I
Please send an email to <ksai AT cs DOT wisc DOT edu>.
Saisuresh Krishnakumaran, Sai Arunachalam, - 'Towards economic
Trace Caches-a profile based approach', Poster session of the 10th International Conference on High
Performance Computing 2003, Hyderabad,
Abstract: Our scheme lays
out a profile-based approach to increase the efficiency of the trace
cache. The application program is profiled on its first run and the
resulting profile in used thenceforth for future runs, provided the run
time environment does not change. The program is partitioned and the
profiles seek to differentiate between the most important and the not
so important traces in each of the subset. This information is
judiciously used to achieve enhanced performance of the trace cache.
support for Transactional Memories."
New architectures open avenues for innovation in compiler technologies. With increasing interests in Transactional Memories as a mechanism for concurrency management in multiprocessors, compiler techniques especially optimization needs to be revisited. For this project we explore some optimizations that could benefit from the atomicity property of transactions. We investigate how traditional optimizations change and also explore a new way to use transactional architectures.
"Exploring I/O in a Virtual Machine
virtualized environments, an operating system may
not have complete knowledge about its resources, as it sees only
virtualized forms of physical resources. In this paper, we show how the
lack of information about a disk's activity can affect performance of a
virtual machine. Specifically, we address how information about disk
idleness can be passed to virtual machines so that idle disk periods
can be effectively utilized to maximize disk bandwidth. The main focus
of this paper is the discussion of various mechanisms that could be
applicable in a virtualized environment in order to effectively expose
such information and exercise control. We discuss designs to infer the
number of dirty pages in each domain from the VMM, and to coerce a
domain to flush its dirty pages. Finally, we present evaluation of
"Reducing Request Bandwidth in Token Coherence."
Conventional query optimizers
assume that all data are disk resident while optimizing queries.
Techniques such as Buffer Pool Aware Query Optimization try to attain
better performance by utilizing the contents of the buffer pool. They
have analyzed how data present in the buffer pool can affect the choice
of query plans in an optimizer. However, these techniques still leave a
wider scope for improvement by performing optimization and reordering
as separate phases. In our work, we have shown how reordering these
queries and optimization can be combined in a single phase to gain
significant performance improvement. Reordering queries minimizes the
total IO cost by utilizing the existing buffer pool contents. We have
developed two heuristics to reorder the queries and experimentally
validated that one of them actually outperforms the optimal algorithm,
when cost of computing the optimal order is included.
and Implementation of Continual Flow Pipelines (CFP)."
Large instruction window
processors can achieve high performance by supplying more instructions
during long latency load misses, thus effectively hiding these
latencies. Continual Flow Pipeline (CFP) architectures provide
high-performance by effectively increasing the number of actively
executing instructions without increasing the size of the
cycle-critical structures. A CFP consists of a Slice Processing Unit
which stores missed loads and their forward slices inside a Slice Data
Buffer. This makes it possible to open up the resources occupied by
these idle instructions to new instructions. In this project, we have designed and
implemented CFP in Simplescalar. We have
compared conventional pipelines to CFPs by
running them on various benchmarks in the SPEC integer benchmarks
suite. We also studied the behavior of mispredicted branches dependent
on load misses, which turn out to be the main bottleneck in CFPs. A comparison
of the performance of CFPs with ideal and
non-ideal fetch mechanisms was also analyzed.
"Natural Language Processing."
Core Processor for Parameterized HPL-PD Architecture.”
Architectural Kit (RAK)."
compiler using LEX and YACC."
of Task Scheduling and Interrupt Processing by Microprocessors."
“Device Driver for a virtual CD drive in Linux environment.”
“Simulation of the Control Logic for an Automatic Teller Machine using VHDL.”
”Designed and implemented an Automatic Traffic Controller using Digital circuits.”Miscellaneous
Secured second place in the 2004 ACM North
Central America Programming
| Page last
modified: Monday, 23-May-2005 19:30:01 CDT
Feedback or content questions: send email to - ksai [cs.wisc.edu] -
Technical or accessibility issues: firstname.lastname@example.org
Copyright © 2002, 2003, 2004 The Board of Regents of the University of Wisconsin System.