Registers are specified as $[0-7]. Register aliases are ($sp, $fp, $t0, $t1, $v0, $v1, none, $ra) map to ($0, $1, $2, $3, $4, $5, $6, $7) respectivly. The syntax for the assembler is almost identical to the MIPS RISC assembly syntax with the same pseudo-instructions. Most of the instructions map directly from WISC with a few exceptions. All the immediate instructions (addi, subi, etc.) have the same memonic as the register instruction (add, sub, etc.). So the assembly instruction "add $3, $2, $5" uses the add instruction (opcode = 01000) and "add $3, $2, 14" uses the addi instruction (opcode = 10000).
The assembler also chooses the correct WISC load/store instruction from the input format. There is one load instruction (mnemonic = ld or lw), one store instruction (mnemonic = st or sw), and one load immediate instruction (mnemonic = li).
| Assembler Instruction | WISC Instruction |
| ld $4, -3($2) | LDI $4, $2, -3 (opcode = 11010) |
| lw $4, $2 | LDI $4, $2, 0 (opcode = 11010) |
| ld $4, $2, $3 | LD $4, $2, $3 (opcode = 01010) |
| st $4, 5($2) | STI $4, $2, 5 (opcode = 11011) |
| sw $4, $2 | STI $4, $2, 0 (opcode = 11011) |
| st $4, $2, $3 | ST $4, $2, $3 (opcode = 01011) |
| li $4, 4021 | LUI $4, (upper 16 bits = 0f) LLI $4, (lower 16 bits = b5) |
| ld+ $4, 5($2) | LD+ $4, $2, 5 |
| lw+ $4, $2 | LD+ $4, $2, 0 |
Any instruction can be prefixed with a label in the same format as MIPS (ex. "loop: beqz $4, end_loop"). And then all the branches, the j, and jal instructions take as a last argument a label to branch to. All the zero branch instructions from WISC are avaliable (beqz, bltz, blez, bnez, bdne)
The assembler provides a bunch of useful instructions that are not WISC instructions.
The branches and the st pseudo-instructions need register $6 to synthesize so don't keep a value you need in $6 when using them. Along with beq all the normal comparisons (beq, blt, bgt, ble, bge, bne) are avaliable. Each pseudo-branch takes two registers and a label as operands. These are implemented by two instructions, first the two registers are subtracted and the result is stored in register 6 and then register 6 is compared to zero. The bgt and bge switch the order of subtraction and then use bltz and blez. Out of all MIPS branches, the only two missing are bgtz and bgez becuase they don't have simple mappings to the WISC instructions.
With the two compiler directives .text and .data switching between declaring instructions and data. The layout of memory is first all the instructions and then after that the static data area. I suggest when using the stack you initialize $sp to FFFF and grow the stack down from the top of memory to avoid running over the instructions and data..data a: .space 1 #declares a as one word space x: .space 4 #declares x as four word space y: .space 3 #declares y as three word space z: .word 0x4A21 #declares z as a word, with initial value 0x4A21 t: .word 143 #declares t as a word, with initial value 143 str: .asciiz "This is cool.\"\n\tWith a \'second\' line even\\" str1: .asciiz "Hi" str2: .asciiz "" .text (lots of instructions)... .data r: .space 1 num: .word 15 .text (more instructions)...
And to run the assembler...% cd ~ % tar xvzf wisc-assembler.tar.gz % cd wisc-assembler % make
In the CS computer labs, you can optionally add wiscas to your ~/bin directory% ~/wisc-assembler/wiscas <assembly file>
The assembler will produce two files, a variable and instruction helper file (.help) and a file with the memory to load into the simulator (.mem). The help file is a helper for debugging: it contains a lists every variable and its address and then a list of every instruction address and the coorisponding line number in the source file.% cp ~/wisc-assembler/wiscas ~/bin % cd ~/path/to/552/stuff % wiscas <assembly file>